search for: optlevel

I see the BackendUtil.cpp of Clang creates the TargetMachine with the optimization level based on below mentioned logic CodeGenOpt::Level OptLevel = CodeGenOpt::Default; switch (CodeGenOpts.OptimizationLevel) { default: break; case 0: OptLevel = CodeGenOpt::None; break; case 3: OptLevel = CodeGenOpt::Aggressive; break; } As per my understanding, the correspondence between optimization level and CodeGenOpt is as below O0 -...

..., nv50_ir::CG_STAGE_PRE_SSA); @@ -1257,13 +1257,13 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info) prog->convertToSSA(); if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE) - prog->print(); + prog->print(info->omitLineNum); prog->optimizeSSA(info->optLevel); prog->getTarget()->runLegalizePass(prog, nv50_ir::CG_STAGE_SSA); if (prog->dbgFlags & NV50_IR_DEBUG_BASIC) - prog->print(); + prog->print(info->omitLineNum); if (!prog->registerAllocation()) { ret = -4; diff --git a/src/gallium/drivers/nou...

.../nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index ffd53c9cd3..604a22ba89 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -82,6 +82,7 @@ struct nv50_ir_prog_info uint8_t optLevel; /* optimization level (0 to 3) */ uint8_t dbgFlags; + bool omitLineNum; struct { int16_t maxGPR; /* may be -1 if none used */ diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp index 9145801b62..eb7e9057...

...; // Canonicalize indvars MPM.add(createLoopIdiomPass()); // Recognize idioms like memset. addExtensionsToPM(EP_LateLoopOptimizations, MPM); MPM.add(createLoopDeletionPass()); // Delete dead loops .. if (!DisableUnrollLoops) MPM.add(createSimpleLoopUnrollPass(OptLevel)); // Unroll small loops I see -debug-pass=Structure output: Scalar Evolution Analysis Loop Pass Manager Induction Variable Simplification Recognize loop idioms Delete dead loops Unroll loops MergedLoadStoreMotion Which is in line...

...t; On Jan 4, 2017, at 4:03 PM, Sumanth Gundapaneni via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >> >> I see the BackendUtil.cpp of Clang creates the TargetMachine with >> the optimization level based on below mentioned logic >> >> CodeGenOpt::Level OptLevel = CodeGenOpt::Default; >> switch (CodeGenOpts.OptimizationLevel) { >> default: break; >> case 0: OptLevel = CodeGenOpt::None; break; >> case 3: OptLevel = CodeGenOpt::Aggressive; break; >> } >> >> As per my understanding, the correspondence between optimiz...

What if in the registration interface we had three options: skippable, not skippable, and run at OptLevel::None. We'd need some way to communicate the OptLevel::None to the pass, but that doesn't seem terrible. -Andy -----Original Message----- From: David Greene [mailto:dag at cray.com] Sent: Monday, October 01, 2018 7:01 AM To: Fedor Sergeev <fedor.sergeev at azul.com> Cc: Kaylor, An...

On 10/01/2018 08:39 PM, David Greene wrote: > "Kaylor, Andrew" <andrew.kaylor at intel.com> writes: > >> What if in the registration interface we had three options: skippable, >> not skippable, and run at OptLevel::None. > I kind of like this idea. If necessary, the pass could even query the > target (or some other entity) about what OptLevel::None means. > > If we have such query hooks, do we need "not skippable?" If a pass is > not skippable, then running at OptLevel::None should...

...I try to debug "target does not support mc emission" in linux (the same code executes OK in windows): Below is a snippet extracted from this method, if (UseMCJIT && ExecutionEngine::MCJITCtor) { ExecutionEngine *EE = ExecutionEngine::MCJITCtor(M, ErrorStr, JMM, OptLevel, AllocateGVsWithCode, TM); if (EE) return EE; } else if (ExecutionEngine::JITCtor) { ExecutionEngine *EE = ExecutionEngine::JITCtor(M, ErrorStr, JMM, OptLevel, AllocateGVsWithCode, TM); i...

..., nv50_ir::CG_STAGE_PRE_SSA); @@ -1257,13 +1257,13 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info) prog->convertToSSA(); if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE) - prog->print(); + prog->print(info->omitLineNum); prog->optimizeSSA(info->optLevel); prog->getTarget()->runLegalizePass(prog, nv50_ir::CG_STAGE_SSA); if (prog->dbgFlags & NV50_IR_DEBUG_BASIC) - prog->print(); + prog->print(info->omitLineNum); if (!prog->registerAllocation()) { ret = -4; diff --git a/src/gallium/drivers/nou...

...be optimized in Combine(AfterLegalizeTypes). But LegalizeTypes() did not change anything and Combine(AfterLegalizeTypes) was not called. Vector legalization that comes afterwards just scalarized the operation. SelectionDAGISel::CodeGenAndEmitDAG() .. CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); bool Changed; Changed = CurDAG->LegalizeTypes(); if (Changed) { CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); } The problem does not exist if the function is bigger and something was changed on LegalizeTypes() stage. I think that Combine(AfterLegalizeTypes) shou...

...e code emitted. This method should returns true if fails. + /// It fills the MCContext Ctx pointer used to build MCStreamer. + /// + virtual bool addPassesToEmitMC(PassManagerBase &PM, + MCContext *&Ctx, + CodeGenOpt::Level OptLevel, + bool DisableVerify = true) { + return true; + } Ditto. + /// get machine code emitted. This method should returns true if fails. + /// It fills the MCContext Ctx pointer used to build MCStreamer. + /// + virtual bool addPassesToEmitMC(PassManagerBase &a...

Hi All, I want to use Optimization Level options in tailDuplicate() API from TailDuplicator.cpp file to restrict splice() function. With -Oz option this splice() API is duplicating the RET instruction in predecessor blocks. Could anyone please give your suggestions to get OPTLevel Options(which object will carry OptLevel Options in this stage?) in this level. Thanks & Regards, Ramakota Reddy. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender imme...

Hi Ankur, > The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( > "llc -help" doesn't list it ). as far as I remember, displaying DAGs during compilation is only enabled in "debug builds" [1] of LLVM. You probably have to re-configure and re-compile LLVM to enable this feature. Best regards, Christoph [1]

...on come from? I couldn't find it in the MASS table of contents on CRAN. Thanks in advance for any help you can give! ######DATASET1, ORIGINAL ORDER > pprfile.ppr <- ppr( + award~ + ilogemp+ilogage, + data=dataset1, nterms=1, max.terms=40, optlevel=3, bass=0 + ) > pprfile.ppr Call: ppr.formula(formula = award ~ ilogemp + ilogage, data = dataset1, nterms = 1, max.terms = 40, optlevel = 3, bass = 0) Goodness of fit: 1 terms 2 terms 3 terms 4 terms 5 terms 6 terms 94153840890 97278012020 86500905681 55028...

New patch taking Eli's comments into account. Olivier. On Tue, Jul 20, 2010 at 11:09 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Jul 20, 2010 at 1:36 PM, Olivier Meurant > <meurant.olivier at gmail.com> wrote: >>> Seems reasonable, but I haven't looked at the code yet. I would >>> suggest trying to split your work up into separate

...257,13 +1257,13 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info) > prog->convertToSSA(); > > if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE) > - prog->print(); > + prog->print(info->omitLineNum); > > prog->optimizeSSA(info->optLevel); > prog->getTarget()->runLegalizePass(prog, nv50_ir::CG_STAGE_SSA); > > if (prog->dbgFlags & NV50_IR_DEBUG_BASIC) > - prog->print(); > + prog->print(info->omitLineNum); > > if (!prog->registerAllocation()) { > ret =...

...when the optimization level is set to zero, i.e. the initial ridge terms are accepted without refitting. I encountered this problem in an out-of-sample prediction exercise using predict. But further investigation suggests the issue is with the ppr fit and predict just sppeds up the crash. The other optlevels seem to be OK, but I have not done enough testing to say for sure. I'm using 2.11.1 under the 32-bit Windows XP. I've also tested the codes under a 64-bit Ubuntu and the same problem occurred. By the way, right before Rgui shuts down, the pop-up window suggests it's a runtime error in...

I am trying to understand the SelectionDAG construction from LLVM IR. I have gone through the doc "The LLVM Target-Independent Code Generator" on LLVM site. This gives a great initial overview. However I am unable to catch the actual control flow for the llvm->selectionDag conversion. The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( "llc

getOptLevel() gets the level from TargetMachine which is created by the Backendutil in clang with either "Default", "None" or "Aggressive". Threre is no correspondence for "Less". This boils down to , if I pass "-O1", the Target Machine is created with CodeG...

...he tool). In my case, only the three next commands are possible:myTool option1myTool option2 arg1 arg2 myTool option3 arg1and I don't want a different order is possible, for instance, this is not permitted:myTool arg2 option2 arg1So, I thought about using an enum for this first argument:enum OptLevel{option1, option2, option3};cl::opt<OptLevel> OptionsLevel(cl::Positional, cl::desc("Choose one of these options:"),cl::values(clEnumVal(option1, "..."),clEnumVal(option2, "..."),clEnumVal(option3, "..."), clEnumValEnd),);After that, the rest of argument...