search for: opstr

...it register or a pair of 32 bit registers. In the current implementation this instruction is defined as follows: // Instructions that convert an FP value to 64-bit fixed point. let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in multiclass FFR1_L_M<bits<6> funct, string opstr> { def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; } // Instructions that convert an FP value to 32-bit fixed point. multiclass FFR1_W_M<bits<6> funct, string opstr> { def _S : FF...

...r of 32 bit registers. In the current implementation this instruction is defined as follows: > > // Instructions that convert an FP value to 64-bit fixed point. > let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in > multiclass FFR1_L_M<bits<6> funct, string opstr> { > def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; > def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; > } > > // Instructions that convert an FP value to 32-bit fixed point. > multiclass FFR1_W_M<bits<6> funct, stri...

I'm building this with llvm-c, and accessing these intrinsics via calling the intrinsic as if it were a function. class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : NVPTXInst<(outs regclassOut:$dst), (ins), OpStr, [(set regclassOut:$dst, (IntOp))]>; def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs, int_nvvm_read_ptx_sreg_tid_x>; This me...

...ex example. Your second question is needs be answered first. null_frag causes the pattern to be dropped. Now having covered that the reason the operands are in the order they are is because the only instruction that doesn't use null_frag is this one defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)), x86memop, RC, OpVT, mem_frag, OpNode> Which specifies the operand order as 213 thus why they are 2, 1, 3 in the pattern. ~Craig On Fri, Nov 16, 2012 at 12:19 AM, Anitha B Gollamudi < anitha.boyapati at gmail.com> wrote: > O...

...g -emit-llvm ...) and check out how it differs from working examples, for instance, nvptx regression tests. ----- Original message ----- > I'm building this with llvm-c, and accessing these intrinsics via calling > the intrinsic as if it were a function. > > class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : >            NVPTXInst<(outs regclassOut:$dst), (ins), >                              OpStr, >                  [(set regclassOut:$dst, (IntOp))]>; > > def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;",...

...all i32 @llvm.nvvm.read.ptx.sreg.tid.x() Pete On Fri, Mar 1, 2013 at 11:51 AM, Timothy Baldridge <tbaldridge at gmail.com> wrote: > I'm building this with llvm-c, and accessing these intrinsics via calling > the intrinsic as if it were a function. > > class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : > NVPTXInst<(outs regclassOut:$dst), (ins), > OpStr, > [(set regclassOut:$dst, (IntOp))]>; > > def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs, > int_nvvm_read...

...gt; Pete > > > On Fri, Mar 1, 2013 at 11:51 AM, Timothy Baldridge <tbaldridge at gmail.com> > wrote: > > I'm building this with llvm-c, and accessing these intrinsics via calling > > the intrinsic as if it were a function. > > > > class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : > > NVPTXInst<(outs regclassOut:$dst), (ins), > > OpStr, > > [(set regclassOut:$dst, (IntOp))]>; > > > > def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32R...

..."PHRASE"; break; case Xapian::Query::OP_ELITE_SET: name = "ELITE_SET"; break; + case Xapian::Query::OP_MATCH_NOTHING: name = "MATCH_NOTHING"; break; } return name; } @@ -211,6 +217,9 @@ if (tname.empty()) return "<alldocuments>" + opstr; return tname + opstr; } + if (op == Xapian::Query::OP_MATCH_NOTHING) { + return "<nodocuments>"; + } opstr = " " + get_op_name(op) + " "; if (op == Xapian::Query::OP_NEAR || @@ -414,6 +423,9 @@ return qint_from_vector(Xapia...

On 16 November 2012 13:41, Anitha B Gollamudi <anitha.boyapati at gmail.com> wrote: > Hi, > > I have a simple question w.r.t the order of operands used in dag > pattern matching in target files. Some of them seem intuitive. But I > want to get it clarified anyway. I am using a pattern from > X86InstrFMA.td in the below example. Consider FMA3 pattern > (simplified). >

Hi, I have a simple question w.r.t the order of operands used in dag pattern matching in target files. Some of them seem intuitive. But I want to get it clarified anyway. I am using a pattern from X86InstrFMA.td in the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand

Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 

Timothy, Those calls to compute grid intrinsics are definitely wrong. In ptx code they should end up into reading special registers, rather than function calls. Try to take some working example and figure out the LLVM IR differences between it and the result of your compiler. - D. ----- Original message ----- > I've written a compiler that outputs PTX code, the result seems fairly >

I've written a compiler that outputs PTX code, the result seems fairly reasonable, but I'm not sure the intrinsics are getting compiled correctly. In addition, when I try load the module using CUDA, I get an error: CUDA_ERROR_NO_BINARY_FOR_GPU. I'm running this on a 2012 MBP with a 640M GPU. PTX Code (for a mandelbrot calculation): // // Generated by LLVM NVPTX Back-End //

Now it's a good time to introduce the new tool 'o2info' since kernel part of OCFS2_IOC_INFO ioctl has been pulld upstream by linus. The following 6 patches have already got sunil's SOBs, and now they're trying to attract more reviewers before it goes to central repo with a modification of getting manual pages being introduced.