Displaying 20 results from an estimated 32 matches for "opno".
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2012 Nov 24
2
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
...n I chose was to use PreprocessISelDAG() to decide which operands needed spilling to memory and then to store and load them from a new stack slot. This seems to work OK for me, though I'm no expert in such matters - perhaps someone more knowledgeable could comment?
>
> Given that operand OpNo of Node needs to be a load, this is the code snippet I used:
>
> // Now we know which node to spill, perform the spill.
> SDValue SpillVal = Node->getOperand(OpNo);
> SDValue SpillSlot = CurDAG->CreateStackTemporary(SpillVal.getValueType());
> int FI = cast<...
2012 Nov 24
0
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
...to use PreprocessISelDAG() to decide which operands
> needed spilling to memory and then to store and load them from a new stack
> slot. This seems to work OK for me, though I'm no expert in such matters -
> perhaps someone more knowledgeable could comment?
>
> Given that operand OpNo of Node needs to be a load, this is the code
> snippet I used:
>
> // Now we know which node to spill, perform the spill.
> SDValue SpillVal = Node->getOperand(OpNo);
> SDValue SpillSlot = CurDAG->CreateStackTemporary(SpillVal.getValueType());
> int FI = cast...
2010 Jul 07
0
[LLVMdev] LLC Bug x86 with thread local storage
...vel at TPOFF, %ecx
or
- movq $tm_nest_level at TPOFF, %rcx
or
- movl tm_nest_level at TPOFF, %ecx
Otherwise, Is there a way to remove this $ character?
I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
O << '%' << getRegisterName(Op.getReg());
} else if (Op.isImm()) {
...
} else {
assert(Op.isExpr() && "unknow...
2018 Feb 07
2
retpoline mitigation and 6.0
...k;
}
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ if (emit_pct)
+ O << '%';
+
+ O << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}
@@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print DImode register
+ case 'V': // Print native register without '%'
if (MO.isReg())
return printAsmMRegister(*this, MO, ExtraCode[0], O);...
2010 Jun 22
2
[LLVMdev] LLC Bug x86 with thread local storage
On 06/21/2010 08:21 PM, Eric Christopher wrote:
> On Jun 21, 2010, at 2:56 AM, Patrick Marlier wrote:
>
>
>> Hello,
>>
>> This bug affects all LLVM versions from 2.6 to trunk :
>> http://llvm.org/bugs/show_bug.cgi?id=5081
>>
>> The workaround I found is to add this :
>>
>> Index: lib/Target/X86/X86Instr64bit.td
>>
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
...e branch which is
the target label. I make a call from the .td for the branch instruction
which calls a routine in MipsMCCodeEmmitter.cpp. That routine
##############################################################
unsigned MipsMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {
unsigned Reg = MO.getReg();
unsigned RegNo = getMipsRegisterNumbering(Reg);
return RegNo;
} else if (MO.isImm()) {
return static_cast<unsigned&g...
2010 Jul 07
4
[LLVMdev] LLC Bug x86 with thread local storage
...ople.redhat.com/drepper/tls.pdf
it would be movl tm_nest_level at TPOFF, %ecx
> Otherwise, Is there a way to remove this $ character?
>
> I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
>
> void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
> raw_ostream &O) {
> const MCOperand &Op = MI->getOperand(OpNo);
> if (Op.isReg()) {
> O << '%' << getRegisterName(Op.getReg());
> } else if (Op.isImm()) {
> ...
> } else {
> assert(Op.isExpr()...
2011 Oct 07
3
[LLVMdev] VirtRegRewriter.cpp: LocalRewriter::ProcessUses()
...s inserted by a partial def below
1930d1923
< }
1941,1951c1934,1937
< MachineOperand newMO = MachineOperand::CreateReg(VirtReg,
< false, // isDef
< true); // isImplicit
< MI.addOperand(newMO);
< int opNo; //FIX: the opNo should be returned by addOperand()
< for(unsigned oi=0;oi<MI.getNumOperands();oi++)
< if(MI.getOperand(oi).isIdenticalTo(newMO)){
< opNo=oi;
< break;
< }
< VirtUseOps.insert(VirtUseOps.begin(), opNo);
---
> VirtUseOps.i...
2019 Mar 25
2
Printing PC-relative offsets - how to get the instruction length?
Hi
In my MC6809 backend, in llvm/lib/Target/MC6809/InstPrinter/MC6809InstPrinter.cpp, I have the routine
void MC6809InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
ZZ
if (Op.isImm()) {
int64_t Imm = Op.getImm() + 2; <<<========================
O << "$";
if (Imm >= 0)
O << '+';
O << Imm;
} else {
assert(Op.i...
2010 Feb 22
2
[LLVMdev] Patch - big stackframes on SPU
Hello all,
currently the SPU backend does not handle big stack frames (>16*511
bytes) nicely. llc asserts on malformed machine instructions.
(Assertion `MI->getOperand(OpNo).isImm() && "printDFormAddr first
operand is not immediate")
E.g. the function:
define i32 @foo() nounwind {
entry:
%retval = alloca i32
%big_data = alloca [1000 x i32]
store i32 3840, i32* %retval, align 4
br label %return
return:
%retval2 = load i32* %retva...
2012 Dec 02
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
...t sure it's *volatile* that let you get a new result, you might
want to try change some other parameters and check what it turns out.
Regards.
2012/12/2 Joseph Pusdesris <joe at pusdesris.com>
>
> So I think I have made some progress.
> SDValue dupVal = consumer->getOperand(OpNo);
> LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode();
>
> SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(), dupVal.getDebugLoc(),
> dupVal.getOperand(0), dupVal.getOperand(1),
> dupNode->getPointerInfo(),...
2010 Jul 07
0
[LLVMdev] LLC Bug x86 with thread local storage
...>
> it would be movl tm_nest_level at TPOFF, %ecx
>
>> Otherwise, Is there a way to remove this $ character?
>>
>> I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
>>
>> void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
>> raw_ostream&O) {
>> const MCOperand&Op = MI->getOperand(OpNo);
>> if (Op.isReg()) {
>> O<< '%'<< getRegisterName(Op.getReg());
>> } else if (Op.isImm()) {
>> ...
>> }...
2018 Feb 07
0
retpoline mitigation and 6.0
...; X86ATTInstPrinter::getRegisterName(Reg);
> + if (emit_pct)
> + O << '%';
> +
> + O << X86ATTInstPrinter::getRegisterName(Reg);
> return false;
> }
>
> @@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr
> *MI, unsigned OpNo,
> case 'w': // Print HImode register
> case 'k': // Print SImode register
> case 'q': // Print DImode register
> + case 'V': // Print native register without '%'
> if (MO.isReg())
> return printAsmMRegister...
2018 Mar 26
0
wrong imm value for branch conditions..
...;*
*{*
* let PrintMethod = "printPCRelImmOperand";*
* let EncoderMethod = "getBranchTargetOpValue";*
* let OperandType = "OPERAND_PCREL";*
* let DecoderMethod = "DecodeBranchTarget";*
*}*
*getBranchTargetOpValue**(const MCInst &MI, unsigned OpNo,*
* SmallVectorImpl<MCFixup> &Fixups,*
* const MCSubtargetInfo &STI) const {*
* const MCOperand &MO = MI.getOperand(OpNo);*
* printf("in getBranchTargetOpValue\n");*
*;*
*;*
*;*
* return 0;*
*}*
I have add...
2012 Dec 02
0
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
So I think I have made some progress.
SDValue dupVal = consumer->getOperand(OpNo);
LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode();
SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(),
dupVal.getDebugLoc(),
dupVal.getOperand(0), dupVal.getOperand(1),
dupNode->getPointerInfo(),...
2010 Feb 24
0
[LLVMdev] Patch - big stackframes on SPU
On Feb 22, 2010, at 6:08 AM, Kalle.Raiskila at nokia.com wrote:
> Hello all,
>
> currently the SPU backend does not handle big stack frames (>16*511
> bytes) nicely. llc asserts on malformed machine instructions.
> (Assertion `MI->getOperand(OpNo).isImm() && "printDFormAddr first
> operand is not immediate")
Sounds fine to me in general. Please write a testcase for this though. Also, this patch causes the CodeGen/CellSPU/call.ll regression test to fail. Please investigate and send an updated patch (with a testcase),...
2009 Jun 03
5
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
...t; ACPV->getModifier() << ")";
if (ACPV->getPCAdjustment() != 0) {
O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
@@ -695,12 +707,31 @@
}
}
+
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNo) {
- const MachineOperand &MO1 = MI->getOperand(OpNo);
- const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
- unsigned JTI = MO1.getIndex();
- O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << '_'...
2012 Dec 01
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
Hi, I am writing an llvm target and I need both loads for isel reasons, but
I am struggling to find the right way. I have been trying to
use DAG.getLoad() to make a copy, then just change the operand in the
consumers, but I cannot seem to get all of the arguments needed for that
function in order to make the copy. Any help would be great, thanks!
-Joe
-------------- next part --------------
An
2011 Oct 10
0
[LLVMdev] Adding fixups and relocations late in code generation
...get label. I make a call from the .td for the branch instruction
> which calls a routine in MipsMCCodeEmmitter.cpp. That routine
>
> ##############################################################
> unsigned MipsMCCodeEmitter::
> getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
> SmallVectorImpl<MCFixup> &Fixups) const {
>
> const MCOperand &MO = MI.getOperand(OpNo);
>
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
>
> unsigned RegNo = getMipsRegisterNumbering(Reg);
> return RegNo;
>
> } else if (MO...
2018 Feb 07
0
retpoline mitigation and 6.0
On Wed, 2018-02-07 at 13:16 -0800, Guenter Roeck wrote:
> Here are my exact versions:
> llvm: 3afd566557f3 ("AMDGPU: Add 32-bit constant address space")
> clang: 848874aed95a ("[clang-format] Fix ObjC message arguments formatting.")
OK, mine are slightly newer than that now, but I now get a working 64-
bit defconfig build. It'll still break with any PV