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...start? I believe this broke after I issued some set auth.allow commands: # gluster volume set oem-shared auth.allow 10.54.54.57,10.54.54.160,10.54.54.161,10.54.54.213,10.54.54.214,10.22.9.73,10.22.9.74 Kind regards, Sophie [2017-06-20 13:28:24.052623] E [glusterd-op-sm.c:207:glusterd_get_txn_opinfo] 0-: Unable to get transaction opinfo for transaction ID : e68a4c2b-0b76-4057-bceb-ba4bc60949e0 [2017-06-20 13:28:24.052647] E [glusterd-op-sm.c:6470:glusterd_op_sm] 0-management: Unable to get transaction's opinfo [2017-06-20 13:28:24.053543] E [glusterd-op-sm.c:207:glusterd_get_txn_opinfo...

...vm::TargetLowering::getRegForInlineAsmConstraint(), the "r" constraint (i.e. TargetLowering::C_RegisterClass) isn't handled and the function returns <pair>(0, NULL). However, it is explicitly called for that constraint by llvm::SelectionDAGLowering::visitInlineAsm(): if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs); Assuming the correct fix is to enhance llvm::TargetLowering::getRegForInlineAsmConstraint(), can someone give me some pointers as to how to fix it? I have no experience...

...llo, While I was trying to cross-compile Linux OMAP kernel with llvm, I have the following error message. CC arch/arm/kernel/traps.o cc1: /home/wonjeon/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp:5388: void llvm::SelectionDAGLowering::visitInlineAsm(llvm::CallSite): Assertion `(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && "Unknown constraint type!"' failed. arch/arm/kernel/traps.c:748: internal compiler error: Aborted Please submit a full bug report, with preprocessed source if...

...ue() is the following: 3817 // This is a reference to a register class that doesn't directly correspond 3818 // to an LLVM register class. Allocate NumRegs consecutive, available, 3819 // registers from the class. 3820 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3821 OpInfo.ConstraintVT); Is it me or is the comment not really applicable to this particular case? thanks, -- Marcel Moolenaar xcllnt at mac.com

On Tue, 20 May 2008, Marcel Moolenaar wrote: > On May 20, 2008, at 1:45 PM, Marcel Moolenaar wrote: >> The following IR is causing the assert: The issue here is that the IA64 backend doesn't have inline asm support yet. This should be pretty easy to add. Take a look at the X86 version: X86TargetLowering::getRegForInlineAsmConstraint it just maps "r" onto the GPR

...to be touched by the dynamic linker even though it's ultimately read-only, and data that cannot be shared between multiple processes using LLVM. It turns out that a solid ~1.3MB of that data is in the tablegen'd MCInstrDesc tables - there a pointers for ImplicitUses, ImplicitDefs, and OpInfo that need to be relocated. This can be fixed of course by having target-global arrays for those structures referenced by MCInstrInfo (and hence TargetInstrInfo), and only storing offsets into those global arrays in MCInstrDesc. The downside is that several relevant accessors need to be augmente...

...it's >> ultimately read-only, and data that cannot be shared between multiple >> processes using LLVM. >> >> It turns out that a solid ~1.3MB of that data is in the tablegen'd >> MCInstrDesc tables - there a pointers for ImplicitUses, ImplicitDefs, and >> OpInfo that need to be relocated. >> >> This can be fixed of course by having target-global arrays for those >> structures referenced by MCInstrInfo (and hence TargetInstrInfo), and only >> storing offsets into those global arrays in MCInstrDesc. >> >> The downside is t...

...-compile Linux OMAP kernel with llvm, I have the > following error message. > > CC arch/arm/kernel/traps.o > cc1: > /home/wonjeon/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp:5388: void > llvm::SelectionDAGLowering::visitInlineAsm(llvm::CallSite): Assertion > `(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || > OpInfo.ConstraintType == TargetLowering::C_Register) && "Unknown constraint > type!"' failed. > arch/arm/kernel/traps.c:748: internal compiler error: Aborted > Please submit a full bug report, > with p...

...e Linux OMAP kernel with llvm, I > have the following error message. > > CC arch/arm/kernel/traps.o > cc1: /home/wonjeon/llvm/lib/CodeGen/SelectionDAG/ > SelectionDAGBuild.cpp:5388: void > llvm::SelectionDAGLowering::visitInlineAsm(llvm::CallSite): > Assertion `(OpInfo.ConstraintType == TargetLowering::C_RegisterClass > || OpInfo.ConstraintType == TargetLowering::C_Register) && "Unknown > constraint type!"' failed. > arch/arm/kernel/traps.c:748: internal compiler error: Aborted > Please submit a full bug report, > wi...

...set starting at operand 2. There does not seem to be any way to obtain the offset to the start of a memory reference in an X86 MachineInstr. Tablegen code is able to determine the offset when it generates the X86GenAsmWriter.inc file at build time. That code obtains the offset indirectly from the OpInfo table entry for an opcodes, which involves extracting a bit field from the OpInfo Entry, then using the extracted code in a switch statement to print out the operands for a particular class of instruction. Would you know if there is a way, given a MachineInstr, to obtain the address offset? Or,...

...m, I >> have the following error message. >> >> CC arch/arm/kernel/traps.o >> cc1: /home/wonjeon/llvm/lib/CodeGen/SelectionDAG/ >> SelectionDAGBuild.cpp:5388: void >> llvm::SelectionDAGLowering::visitInlineAsm(llvm::CallSite): >> Assertion `(OpInfo.ConstraintType == >> TargetLowering::C_RegisterClass || OpInfo.ConstraintType == >> TargetLowering::C_Register) && "Unknown constraint type!"' failed. >> arch/arm/kernel/traps.c:748: internal compiler error: Aborted >> Please submit a full bug r...

...et/emit the operand. > unsigned VReg = getVR(Op, VRBaseMap); > assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); > const MCInstrDesc &MCID = MIB->getDesc(); > bool isOptDef = IIOpNum < MCID.getNumOperands() && > MCID.OpInfo[IIOpNum].isOptionalDef(); > // If the instruction requires a register in a different class, create > // a new virtual register and copy the value into it, but first attempt to > // shrink VReg's register class within reason. For example, if VReg == GR32 > // and II requires...

...>> unsigned VReg = getVR(Op, VRBaseMap); >> assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); >> const MCInstrDesc &MCID = MIB->getDesc(); >> bool isOptDef = IIOpNum < MCID.getNumOperands() && >> MCID.OpInfo[IIOpNum].isOptionalDef(); >> // If the instruction requires a register in a different class, create >> // a new virtual register and copy the value into it, but first attempt >> to >> // shrink VReg's register class within reason. For example, if VReg == >>...

...>> unsigned VReg = getVR(Op, VRBaseMap); >> assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); >> const MCInstrDesc &MCID = MIB->getDesc(); >> bool isOptDef = IIOpNum < MCID.getNumOperands() && >> MCID.OpInfo[IIOpNum].isOptionalDef(); >> // If the instruction requires a register in a different class, create >> // a new virtual register and copy the value into it, but first attempt to >> // shrink VReg's register class within reason. For example, if VReg == GR32 >> //...

...ith llvm, I have >> the following error message. >> >> CC arch/arm/kernel/traps.o >> cc1: >> /home/wonjeon/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp:5388: void >> llvm::SelectionDAGLowering::visitInlineAsm(llvm::CallSite): Assertion >> `(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || >> OpInfo.ConstraintType == TargetLowering::C_Register) && "Unknown constraint >> type!"' failed. >> arch/arm/kernel/traps.c:748: internal compiler error: Aborted >> Please submit a full bug repor...

...nstr_asm # "\t\t$r1, $addr, " # info.sizeStr, [(set info.regClass:$r1, (load ADDR_SHLI:$addr))], itin > { } The other related definitions are: // This class provides load/store address format selection support // class Addr< int numArgs, string funcName, dag opInfo > : Operand<i64>, ComplexPattern< i64, numArgs, funcName, [], [SDNPWantParent] > { let MIOperandInfo = opInfo; } let PrintMethod = "printMemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$...

..., 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); > else > BuildMI(... TargetOpcode::COPY...) > > The condition is trying to reset the reg class if the DstRC reg class is valid for the operand num of the machine instruction. If the NewVReg register class is...

...sVirtualRegister(VReg) && "Not a >>>>>>> vreg?"); >>>>>>> const MCInstrDesc &MCID = MIB->getDesc(); >>>>>>> bool isOptDef = IIOpNum < MCID.getNumOperands() && >>>>>>> MCID.OpInfo[IIOpNum].isOptionalDef(); >>>>>>> // If the instruction requires a register in a different class, >>>>>>> create >>>>>>> // a new virtual register and copy the value into it, but first >>>>>>> attempt to >&gt...

...(VReg) && "Not a >>>>>>>> vreg?"); >>>>>>>> const MCInstrDesc &MCID = MIB->getDesc(); >>>>>>>> bool isOptDef = IIOpNum < MCID.getNumOperands() && >>>>>>>> MCID.OpInfo[IIOpNum].isOptionalDef(); >>>>>>>> // If the instruction requires a register in a different class, >>>>>>>> create >>>>>>>> // a new virtual register and copy the value into it, but first >>>>>>>> at...

...; "Not a >>>>>>>>> vreg?"); >>>>>>>>> const MCInstrDesc &MCID = MIB->getDesc(); >>>>>>>>> bool isOptDef = IIOpNum < MCID.getNumOperands() && >>>>>>>>> MCID.OpInfo[IIOpNum].isOptionalDef(); >>>>>>>>> // If the instruction requires a register in a different class, >>>>>>>>> create >>>>>>>>> // a new virtual register and copy the value into it, but first >>>>>&gt...