search for: opidx

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand";

...do something to not crash on the IR otherwise, which is part of the problem I’m trying to solve. > > Why not simply add a function to TTI that tells you whether a particular Value is a valid n-th argument to the given intrinsic? > Something like > if (TTI.isValidArgument(IntOpc, Val, OpIdx)) > Int->setOperand(Val, OpIdx); > This is required for correctness, so TTI is not appropriate. Reasonably implementing this would still require adding something in TableGen (which then just brings you back to adding an attribute). I would also like to be able to rely on this for emis...

Hi, I would like to solve the longstanding need for a way to indicate which parameters to an intrinsic are required to be immediates. It should be possible to declare in tablegen which parameters must be a trivial constant, or else the IR is invalid. The verifier could then reject invalid intrinsic calls, so code handling the intrinsics doesn’t need to worry about invalid arguments. Currently

AArch64AddressTypePromotion.cpp does a fair bit of work to help make these things work out well. It could probably be generalized for non-AArch64 targets as per the comment in the file header. > On Jun 26, 2014, at 10:42 AM, Sanjay Patel <spatel at rotateright.com> wrote: > > Cool HW trick. :) > Are those 'sxtw' ops free? > That’ll depend on the details of the

...mitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index 7bfaecc..36d6c5f 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -170,6 +170,7 @@ getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, break; } case AArch64MCExpr::VK_AARCH64_GOT_LO12: + case AArch64MCExpr::VK_AARCH64_GOT_LO12_DARWIN: assert(MemSize == 8 && "Invalid fixup for operation"); FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc; break; @@ -283,6 +284,7 @@ AArch64MCCodeEmitter::...