Displaying 5 results from an estimated 5 matches for "opfl_memref".
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opfl_memrefs
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
.../*2249*/ OPC_CheckPredicate, 6, // Predicate_load
> /*2251*/ OPC_CheckType, MVT::i64,
> /*2253*/ OPC_EmitMergeInputChains1_0,
> /*2254*/ OPC_EmitInteger, MVT::i64, 0,
> /*2257*/ OPC_MorphNodeTo, TARGET_VAL(XSTG::LOADI64_RI),
> 0|OPFL_Chain|OPFL_MemRefs,
> 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,
> // Src: (ld:i64 (XSTGADDR_NORMAL:iPTR
> (tglobaladdr:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>
> - Complexity = 10
> // Dst: (LOADI64_...
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
...7
/*1172*/ OPC_EmitConvertToTarget, 5,
/*1174*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
0|OPFL_Chain,
1/*#VTs*/, MVT::i32, 2/*#Ops*/, 4, 8, // Results =
#9
/*1183*/ OPC_MorphNodeTo, TARGET_VAL(Hexagon::COMBINE_rr),
0|OPFL_Chain|OPFL_MemRefs,
***********************************************
Any hints on how I can track this down ? The MemRefs are to be put on the
COMBINE_rr and not the loads.
Pranav
Qualcomm Innovation Center, (QuIC) is a member of the Code Aurora Forum.
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
Hi,
On the hexagon target, I have written a following combiner pattern.
*********************************************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr
2016 Jun 22
2
LLVM Backend Issues
Thanks Anton and Krzysztof!
Here is the dump using the -debug flag. At this point I am not making much
sense of this, would it be too much to ask if one of you could walk me
through one of these lines?
One thing that I didn't point out is that I never defined any separate
floating point registers, not sure if this will pose any issue?
Thanks again for your time!
Jeff
jeff at