search for: operandinfo

in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint does not appear anywhere in source/lib/Target/X86/* yet TIED_TO occurs in 162 of the OperandInfo's in build/lib/Target/X86/X86GenInstrInfo.inc the question is how d...

Hello all, I've managed to trace an awkward bug down to the MSVC linker incorrectly merging llvm::OperandInfo constants between various backend targets I was linking in to my compiler executable. The bug manifested itself by replacing the operand data structures for target A with the data structures for target B. I have managed to work around this issue by moving the operand definitions from the llvm n...

James_Clayton at scee.net writes: [snip] > This is the first time I've made any patches to llvm - please let me know > if you'd like any more information. Please consider submitting your patch to llvm-commits mailing list, which is the correct place for reviewing patches. Inline the patch in your message, don't post links. OTOH, you may be interested on the LLVM coding

On Fri, Aug 17, 2012 at 10:29 AM, Óscar Fuentes <ofv at wanadoo.es> wrote: > James_Clayton at scee.net writes: > > [snip] > >> This is the first time I've made any patches to llvm - please let me know >> if you'd like any more information. > > Please consider submitting your patch to llvm-commits mailing list, > which is the correct place for

...he formula to figure out which bank a register is in is just: r%4 Which brings me to tablegen: We've got this in our specialized ArchInstrInfo.td: // r1 = r2 op r3 // class ArithOp_RR< bits<7> op, string instr_asm, SDNode opNode, OperandInfo info, InstrItinClass itin > : FR3< op, (outs info.regClass:$r1), (ins info.regClass:$r2, info.regClass:$r3), instr_asm # "\t\t$r1, $r2, $r3, " # info.sizeStr, [(set info.regClass:$r1, (opNode info.regClass:$r2, info.regClass:$r3))]...

...on `isa<X>(Val) && "cast<Ty>() argument of incompatible type!"' failed. Looks like the incompatible types are DefInit and Init. The offending line is in this definition: class LoadOpIdx< bits<7> op, string instr_asm, OperandInfo info, InstrItinClass itin=II_LOAD1_RR > // // load: r1 = mem[r2 + (r3 << sizeof(operand) ] // : FR3< op, (outs info.regClass:$r1), (ins ADDR_SHLI:$addr), //<<-this line causes assert instr_asm # "\t\t$r1, $addr, &quo...

On May 19, 2011, at 7:47 AM, Jonas Paulsson wrote: > Hi, > > I am combining 16-bit registers to a 32 bit register in order to make a wide store, as per below: > > 732 %reg16506:hi16<def,dead> = COPY %reg16445<kill>; > 740 %reg16506:lo16<def> = COPY %reg16468<kill>; > 748 %r3<def,dead> = store %reg16506<kill>, %r3, > > As you can

...any COPY's, and this went all the way through, only to find that the register-classes are not used as constraints as in GCC, so the register allocator had no problem with allocating to the wrong register class. Disappointing, after all, this is defined in the .td files and available in the OperandInfo's. Jonas > Subject: Re: [LLVMdev] subregisters, def-kill > From: stoklund at 2pi.dk > Date: Thu, 19 May 2011 15:39:40 -0700 > CC: llvmdev at cs.uiuc.edu > To: jnspaulsson at hotmail.com > > > On May 19, 2011, at 7:47 AM, Jonas Paulsson wrote: > > > Hi, &...

Hi, I am combining 16-bit registers to a 32 bit register in order to make a wide store, as per below: 732 %reg16506:hi16<def,dead> = COPY %reg16445<kill>; 740 %reg16506:lo16<def> = COPY %reg16468<kill>; 748 %r3<def,dead> = store %reg16506<kill>, %r3, As you can see, LiveVariables has marked the high part dead, even though the super-register is used at