Displaying 6 results from an estimated 6 matches for "operand_immedi".
2017 Feb 15
4
Unsigned int displaying as negative
...ffectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why
simm16 matches and uimm16 does not. Here is the pattern if that helps at
all.
So just as a reference:
def simm16 : Operand<i16> {
let DecoderMethod= "DecodeSimm16";
let OperandType = "OPERAND_IMMEDIATE";
}
def uimm16 : Operand<i16> {
let PrintMethod = "printUnsignedImm";
let OperandType = "OPERAND_IMMEDIATE";
}
def immSExt16x : ImmLeaf<i16, [{ return isInt<16>(Imm); }]>;
def immZExt16x : ImmLeaf<i16, [{ return isUInt<16>(Imm); }]&g...
2016 Dec 03
2
Immediate operand for vector instructions
...3} = opcode;
let Inst{26-11} = s16;
}
class REP_1R_DESC_BASE<,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
/* From include/llvm/Target/Target.td:
let OperandType = "OPERAND_IMMEDIATE" in {
...
def i64imm : Operand<i64>; */
dag InOperandList = (ins i64imm:$imm);
string AsmString = "REPEAT_X_TIMES($imm";
list<dag> Pattern = [(int_repeat_x_times i64imm:$imm)];
InstrItinClass It...
2017 Feb 15
5
Unsigned int displaying as negative
...y
>> simm16 matches and uimm16 does not. Here is the pattern if that helps
>> at
>> all.
>>
>> So just as a reference:
>>
>> def simm16 : Operand<i16> {
>> let DecoderMethod= "DecodeSimm16";
>> let OperandType = "OPERAND_IMMEDIATE";
>> }
>>
>> def uimm16 : Operand<i16> {
>> let PrintMethod = "printUnsignedImm";
>> let OperandType = "OPERAND_IMMEDIATE";
>> }
>>
>> def immSExt16x : ImmLeaf<i16, [{ return isInt<16>(Imm); }]>...
2015 Nov 23
3
Qs about TwoOperandAliasConstraint and TIED_TO
in llvm-3.6.2.src
1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file,
let TwoOperandAliasConstraint = "$dst = $rs1" in {
}
I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction,
the question is what am I doing wrong ?
2. I've noticed that TwoOperandAliasConstraint
2017 Feb 15
2
Unsigned int displaying as negative
Thanks for your reply.
We are propagating sign info to tablegen currently using
BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm.
I imagine (I have not looked) they are printed according to instruction in
AsmPrinter.cpp (pure speculation).
I'm still confused as to why 0x7FFF is ok to match 16 bit int but not
0x8000?
Thanks.
On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at
2014 Jun 10
2
[LLVMdev] Regarding Instruction definition in LLVM backend
...Currently I have done the following:
in TARGETRegisterInfo.td file I have defined the registers: MYREG1_NAME and
MYREG2_NAME
in TARGETInstrInfo.td file I have the following definitions:
def simm16 : Operand<i16> {
let DecoderMethod= "DecodeSimm16";
let OperandType = "OPERAND_IMMEDIATE";
}
class SII<bits<6> op, string instr_asm, Operand Imm> :
FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm,
"\t$val"), [], IIAlu> {
let rs = 0;
let rt = 0;
}
def MOV : SII<0x21, "mov", simm16>;
def : TARGETPat&l...