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...e in LiveVariables.cpp which looks at those PHI nodes (line 249 and below) is necessary. The reason I'm asking is that I try to support 64-bit comparison and I do it by generating code like: // if high1 cond high2: goto operand0 // if high1 reverse_cond high2: goto operand1 // if low cond high2: goto operand0 // goto operand1 but this means that operand0 and operand1 (the successor basic blocks) suddenly get more predecessor than recorded in phi nodes, and LiveVariables.cpp asserts on that. Of course, I can add another two basic block whi...

...cond b) then r1 = 1 else r2 = 0 r = phi(r1, r2) > The reason I'm asking is that I try to support 64-bit comparison and I do it > by generating code like: > > // if high1 cond high2: goto operand0 > // if high1 reverse_cond high2: goto operand1 the second if should just be an unconditional branch to operand1: clearly, if (high1 cond high2) is false, the reverse condition is true. > // if low cond high2: goto operand0 > // goto operand1 These would have to go into different blocks, as above you would have...

...MachineBasicBlock *MBB, unsigned LOpcode, unsigned HOpcode) const { const TargetInstrInfo *TII = Subtarget->getInstrInfo(); DebugLoc Loc = MI.getDebugLoc(); const MachineOperand operand0 = MI.getOperand(0); const MachineOperand operand1 = MI.getOperand(1); BuildMI(*MBB, MI, Loc, TII->get(LOpcode)) .add(operand0) .add(operand1); BuildMI(*MBB, MI, Loc, TII->get(HOpcode)) .add(operand0) .add(operand1); MI.eraseFromParent(); return MBB; } Dominique Torette Syste...

Let's say I have the following IR code: 21> %tmp = load i32* @myrand.z, align 4 22> %tmp1 = and i32 %tmp, 5535 23> %tmp2 = mul nsw i32 %tmp1, 36969 24> %tmp3 = ashr i32 %tmp, 16 And I have an Instruction *inst that is the instruction on line 22. then have the code: Use *operand1 = &(inst->getOperandUse(0)); I expect that operand1->getNext() will return the the Use* for %tmp in the instruction on line 24. However, what I get is a null pointer. Why is this exactly? I feel I'm not understanding the point of the Use if I can't even see the very next us...

...those PHI > nodes (line 249 and below) is necessary. > > The reason I'm asking is that I try to support 64-bit comparison and I > do it > by generating code like: > > // if high1 cond high2: goto operand0 > // if high1 reverse_cond high2: goto operand1 > // if low cond high2: goto operand0 > // goto operand1 > > but this means that operand0 and operand1 (the successor basic blocks) > suddenly get more predecessor than recorded in phi nodes, and > LiveVariables.cpp asserts on that. > > Of course, I...

...0 > > r = phi(r1, r2) Ok, I see. > > The reason I'm asking is that I try to support 64-bit comparison and I do > > it by generating code like: > > > > // if high1 cond high2: goto operand0 > > // if high1 reverse_cond high2: goto operand1 > > the second if should just be an unconditional branch to operand1: > clearly, if (high1 cond high2) is false, the reverse condition is true. Actually, you've found a bug: it should be swapped_cond, not reverse_cond. > > but this means that operand0 and operand1 (the successo...

Hi, Let say i am writing a code inside basic block pass and iterating all the instructions inside, and i encountered in this instruction : %3 = add i32 %1, 2 I want to convert this instruction to something like this: add R1, 2, R3 I know the opocode, but i what i need is, the operands %1 and 2 (in this example). I will be grateful if some one will tell me how to do so . -------------- next

Rotem Varon wrote: > Hi, > > Let say i am writing a code inside basic block pass and iterating all > the instructions inside, > and i encountered in this instruction : If you're asking how to get the operands of an Instruction, use the getOperand() method: Value * Operand1 = I->getOperand(0); Value * Operand2 = I->getOperand(1); The LLVM doxygen documentation (http://llvm.org/doxygen/) is an invaluable resource. You may also want to read the Programmer's Guide (http://llvm.org/docs/ProgrammersManual.html). Does this answer your question? -- John T. &...

...s (cs, ds equiv. to r4, r5) // 1 flags register (fl) // // instruction encoding // ++++++++++++++++++++ // // byte 1 byte 2 (optional) // bits [ 7 6 5 4 3 2 1 0 ] [ 7 6 5 4 3 2 1 0 ] // opcode - - - // mod - // operand1 - - - - // operand2 - - - - - - - - // // operand1 is always a register index // operand2 is optional, depending upon the instruction set specified below // the value of mod alters the meaning of any operand2 // 0: operand2 = reg ix /...

On Tue, Mar 4, 2014 at 3:11 PM, Sean Silva <chisophugis at gmail.com> wrote: > On Tue, Mar 4, 2014 at 4:04 PM, Mark Seaborn <mseaborn at chromium.org>wrote: > >> The PNaCl project has implemented various IR simplification passes that >> simplify LLVM IR by lowering complex features to simpler features. We'd >> like to upstream some of these IR passes to