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...s are landing * LLDB * LLVM 11 Backports: * PseudoBranch Patch https://reviews.llvm.org/D84833 * Any other outstanding backport requests? * Evandro's CSR Patch * Any other business? * Next meeting: 20 Aug Regards, Sam -- Sam Elliott Software Team Lead Senior Software Developer - LLVM and OpenTitan lowRISC CIC

Hi Devs, since risc-v has a register $tp which is thread pointer. is it possible to have __builtin_thread_pointer for RISC-V? I am not sure what could be corresponding instructions? ./kamlesh

...se notes as part of reviews? > > James > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- Sam Elliott Software Team Lead Senior Software Developer - LLVM and OpenTitan lowRISC CIC

Hi all developers, I'm changing compiler from gcc to llvm on a RISCV target now. but I found in some case the assembly code generated by llvm is much more than gcc. It cause my program's performance about 40% decrease. The flowing is a simple test code. It shows the problem. We can see than gcc prefer to use pointer to iterate the array, but llvm perfere to use index to iterate

...vm.org/cgi-bin/mailman/listinfo/llvm-dev > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- Sam Elliott Software Team Lead Senior Software Developer - LLVM and OpenTitan lowRISC CIC -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200723/7f2b7e9c/attachment.html>

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Yes - this has been in InstCombine for a long time: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L268 We could say that the canonicalization should be reversed, but that probably uncovers more missing optimizations. The code size concern is legitimate. For example on x86, gcc asm is 2 bytes smaller on this example:

Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V

...n this list since I did not get a reply. > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- Sam Elliott Software Team Lead Senior Software Developer - LLVM and OpenTitan lowRISC CIC -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20201029/f51cedce/attachment.html>

Hi all, I'm aware that LLVM has release notes, but I've never written one myself, despite making at times some fairly significant changes to the various llvm tools. Is there any documentation in LLVM on when a release note is appropriate and how to write one? Should reviewers be asking people to write release notes as part of reviews? James -------------- next part -------------- An HTML

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Am Mi., 1. Juli 2020 um 05:46 Uhr schrieb MyDeveloper Day via llvm-dev <llvm-dev at lists.llvm.org>: > I always knew "polly" was mostly clean too, and actually one of the areas I already test against, (along with lib/Format obviously). You have no other choice. Polly verifies its source formatting as part of check-polly, so every commit that violates formatting will get an

...____________________________ >> > LLVM Developers mailing list >> > llvm-dev at lists.llvm.org >> > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> -- >> Sam Elliott >> Software Team Lead >> Senior Software Developer - LLVM and OpenTitan >> lowRISC CIC >> >> _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > -------------- next part -------------- An HTML attachment was scrubbed... URL:...

Oh, I wasn’t really thinking about devices without an MMU where the addresses are physically separated. Makes sense. This reminds me of rwpi on ARM; it has a sort of similar scheme of referring to data indirectly through a pointer, but it also changes the ABI to keep the pointer in a reserved register. -Eli From: Evandro Menezes <evandro.menezes at sifive.com> Sent: Friday, March 20, 2020

...or a pointer to working documentation. > > With kind regards, Alex > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- Sam Elliott Software Developer - LLVM and OpenTitan lowRISC CIC

Hi everyone, I've been wondering how to correctly build clang/LLVM for the AVR target architecture. Unfortunately documentation is very scarce (or outdated or I didn't find it) and while I've been able to build clang/LLVM for AVR I'm still falling short of compiling an actual binary for the MCU. Here are the steps I've undertaken so far: git clone

For background on these calls, see <http://lists.llvm.org/pipermail/llvm-dev/2019-September/135087.html>. Reminder: the purpose is to co-ordinate between active contributors. If you have support questions etc then it's best to post to llvm-dev. We have a call each Thursday at 4pm GMT, via <https://meet.google.com/ske-zcog-spp>. I've created a shared calendar which may help

The Developer Policy document (https://llvm.org/docs/DeveloperPolicy.html) contains a Section "C API Changes". There is no corresponding section for C++ API Changes. LLVM is somewhat different from most libraries in that the main language is C++ but the C++ API is not guaranteed to be stable in any shape or form from what I understand. I think it would be useful to have a "C++ API