search for: opcodestr

Is it legal to do something like a !strconcat on a non-string entity? That is, is there some operation that will let me do this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // Vector operation emulating scalar (fp) def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32: $src2), !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, $src2}"),...

Dear there, I'm developing an instruction layout like: opcode | rd| ts and its semantics is: rd= rd opcode rs But when I describe it in td file like this: class R<bits<5> Op, string OpcodeStr, list<dag> Pattern> : InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr, "\t$rd, $rs"), Pattern> { bits<5> rd; bits<6> rs; let Opcode=Op; } It complains for 'rd'. I was wondering if there is any standard way of doing this? Thanks...

...r there, >> >> I'm developing an instruction layout like: >> >> opcode | rd| ts >> >> and its semantics is: >> >> rd= rd opcode rs >> >> But when I describe it in td file like this: >> >> class R<bits<5> Op, string OpcodeStr, list<dag> Pattern> >> : InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr, >> "\t$rd, $rs"), Pattern> { >> bits<5> rd; >> bits<6> rs; >> let Opcode=Op; >> } > > You need to use a different input a...

...ome operation that will let me do this (replace > SOME_CONCAT with > an appropriate operator): I don't get it, can you try a simpler example on me? :) -Chris > > > (WARNING! Hacked-up tablegen ahead!) > > multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, > SDNode OpNode> { > // Vector operation emulating scalar (fp) > def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, > FR32: > $src2), > !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, &g...

...classes. > Please look at the documentation for "multiclass" and "defm". In the X86InstrSSE.td file, we have this, which looks very similar to what you have above. let Constraints = "$src1 = $dst" in { multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, bit Commutable = 0> { // Scalar operation, reg+reg. def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strconcat(OpcodeStr, "ss\t{$src2,...

...t_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem, Commutative]>; Untested multiclass! Look for SOME_CONCAT. multiclass myintrinsics<bits<8> opc, string OpcodeStr, Intrinsic Intr> { // Scalar intrinsics def SSrr_Int SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32: $src2), !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (SOME_CONCAT(Intr, _ss) FR32:$src1, FR32: $src2))...

...pattern matching in target files. Some of them seem intuitive. But I want to get it clarified anyway. I am using a pattern from X86InstrFMA.td in the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, ValueType OpVT, PatFrag mem_frag, SDPatternOperator OpNode = null_frag> { def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat...

Bill, Sorry if I wasn't clear enough. I wasn't referring to multiclass's that define other classes, but with using patterns inside of a multiclass to reduce redundant code. For example: multiclass IntSubtract<SDNode node> { def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; def _i32 : Pat<(sub

...ma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>; ... It seems that previous revisions for fma4 intrinsics also followed similar trend. Any idea why? -- Anitha

...class IO_MultSrc<bits<2> op0Type, RegisterClass Src0RC> { dag insDefault = !if(!eq(op0Type, 0b01), (ins SpecialReg:$dst, Src0RC:$a), (ins Src0RC:$a)); ... } multiclass MultSrc1Spec<bits<5> subOpcode, bits<2> op0t, string opcodeStr, RegisterClass RegType> { def _allspecial: MultSrcOneDestInst<subOpcode, op0t, 0b00, IO_MultSrc<op0t, SpecialReg>.outsDefault, IO_MultSrc<op0t, SpecialReg>.insDefault>; ... } multiclass TwoSrcOneDestSpec<bits&l...

...Class = FR32; > ... }; > def X86_i32 : X86ValueType { ... }; > > Then change fp_cvt_scalar_VXSnrr to be something like this: > >> class fp_cvt_scalar_VXSnrr< >> // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr >> bits<8> opc, >> string OpcodeStr, >> SDNode OpNode, >> X86ValueType DstType, >> X86ValueType SrcType, >> int CustomPatterns = 0, >> list<dag> patterns = [], >> string asm = "" >>> : fp_unary_vxs_n_rm_rr< >> opc, DstType.RegClass, > > This lets yo...

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and > "MemOp4" like those of "rm" or "rr" ? > Hey Anitha, The VEX.W bit is used to denote operand order. In other words, this bit allows for a memop to be used as

...lar_xs_scalar64_xs_node_sintrinsic_rm< 0x2D, "cvtsi2ss", sint_to_fp, "cvtsi2ss", "f32", "i32">; [Meanwhile, down in the guts...] class fp_cvt_scalar_VXSnrr< // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr bits<8> opc, string OpcodeStr, SDNode OpNode, string DstType, string SrcType, int CustomPatterns = 0, list<dag> patterns = [], string asm = "" >: fp_unary_vxs_n_rm_rr< opc, !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",!patsubst("^i([0-9]+)",&quo...

...string DecoderMethod = "DecodeMSA128Mem"; } Also, BPF has its own scalar stores and loads (with the standard i64 registers), for example (from https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td): class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode> : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>; However, spills and loads with vector registers, created automatically at the border of basic-blocks use the scalar stores and loads and NOT the vector ones that are also defined. For example, I o...

...c_rm< > 0x2D, "cvtsi2ss", sint_to_fp, "cvtsi2ss", "f32", "i32">; > > [Meanwhile, down in the guts...] > > class fp_cvt_scalar_VXSnrr< > // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr > bits<8> opc, > string OpcodeStr, > SDNode OpNode, > string DstType, > string SrcType, > int CustomPatterns = 0, > list<dag> patterns = [], > string asm = "" >> : fp_unary_vxs_n_rm_rr< > opc, > !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",...

...iles. Some of them seem intuitive. But I > want to get it clarified anyway. I am using a pattern from > X86InstrFMA.td in the below example. Consider FMA3 pattern > (simplified). > > let Constraints = "$src1 = $dst" in { > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > SDPatternOperator OpNode = null_frag> { > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > (ins RC:$src1, RC:$src2, RC:$src3), >...

...EX_W. However VEX_W is not a class, it is an enumerated value. [2]. How does vex_w help in instruction selection in-addition to FMA4 class? [3]. Why does only "rr" and "rm" forms have vex_w but not "mr" ? (Reference) multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC, X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, PatFrag mem_frag> { def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $sr...

On Jun 15, 2009, at 11:33 AM, David Greene wrote: > To reduce redundancy, developers must be able to write generic > patterns > like this: > > [(set DSTREGCLASS:$dst, // rr, rrr > (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))), > (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))], > > The substitution then fills in the appropriate types,

...ed to define a new 17bit type Imm17 in CodeGen/ValueTypes.td/h, or can I cope with the 17 bit immediate elsewhere by perhaps using an i32? OR, can I handle this elsewhere in codegen/instruction selection more elegantly? Apologies for the naivety of my question. multiclass sabre_inst<string opcodestr, bits<5> opcode> { def rr : InstSABRE< opcode, (ops IntRegs:$dst, IntRegs:$src), !strconcat (opcodestr, " $dst, $src")>; def ri: InstSABRE< opcode, (ops IntRegs:$dst, IntRegs:$sr...

...ile functional, is less than ideal in terms of maintenance. In particular, a number of nearly-identical patterns are specified all over for nearly-identical instructions. For example: let Constraints = "$src1 = $dst" in { multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, bit Commutable = 0> { // Scalar operation, reg+reg. def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strc...