search for: opcod

Hi all, I'm trying to compile asterisk on the mainframe (s390 / s390x) and I am running into issues. I was wondering if somebody could give a hand? I'm thinking that I should be able to do this. I have noticed that Debian even has binary RPM's out for Asterisk now. I'm trying to do this on SuSE SLES8 (with the 2.4 kernel). What I see is, an issue that arch=s390 isn't

...km/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index 1420794038642..b54f044c4483b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -575,7 +575,7 @@ init_tmds_reg(struct nvbios_init *init, u8 tmds) * init opcode handlers *****************************************************************************/ -/** +/* * init_reserved - stub for various unknown/unused single-byte opcodes * */ @@ -602,7 +602,7 @@ init_reserved(struct nvbios_init *init) init->offset += length; } -/** +/* * INIT_DONE...

...km/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index 1420794038642..b54f044c4483b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -575,7 +575,7 @@ init_tmds_reg(struct nvbios_init *init, u8 tmds) * init opcode handlers *****************************************************************************/ -/** +/* * init_reserved - stub for various unknown/unused single-byte opcodes * */ @@ -602,7 +602,7 @@ init_reserved(struct nvbios_init *init) init->offset += length; } -/** +/* * INIT_DONE...

...truction { bits<32> TSFlags; } class Domain<bits<2> val> { bits<2> Value = val; } def GenericDomain : Domain<0>; def SSEPackedInt : Domain<1>; def SSEPackedSingle : Domain<2>; def SSEPackedDouble : Domain<3>; class X86Instr<bits<8> opcod> : Instruction { Domain ExeDomain = GenericDomain; let TSFlags{0-7} = opcod; let TSFlags{22-23} = ExeDomain.Value; } class PIInstr<bits<8> opcod> : X86Instr<opcod> { let ExeDomain = SSEPackedInt; } def i1 : X86Instr<0x12>; def i2 : PIInstr<0x34>; def i3 :...

...erand orders for at&t syntax vs intel syntax. Anything after $ matches the name in the outs/in part of the instruction. IIC_SSE_PREFETCH is part of the scheduler system to provide latency/throughput information about the instruction. PD indicates the instruction should be on the 0x0f two byte opcode map with a 0x66 prefix. Most common other values in place of PD TB - 0x0f opcode map no prefix(0x66, 0xf2, 0xf3) and use of one of those prefixes should be ignored by the disassembler. PS - 0x0f opcode map no prefix, but if the disassembler sees a prefix it should not decode to this instruction....

I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead...

...me a clue, perhaps! For the sake of my own edification (and not taking up too much of your time) I will try to generate it myself. I've found the definition of the "I" class at line 358 of llvm/lib/Target/X86/X86InstrFormats.td, which helps a lot. Let's assume I want to produce opcode 0x16 (which I'm using because it doesn't seem to be implemented in gem5 otherwise, and would simply produce a warning). Then my guess is that I should use something like: def CACHEADD : I<0x16, FORMAT, (outs), (ins), ASM, [(int_cache_add)]>, PD; where FORMAT comes...

On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: > I am using lowering instructions and using custom opcodes that I can > more easily directly map to my backend. These opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being confused as a FRAME...

...on was answered completely, in my opinion. This was the key line: def CACHEOP : I<0x06, RawFrm, (outs), (ins), "cache_op", [(int_cache_op)]>; I added this definition to llvm/lib/Target/X86/X86InstrInfo.td. I also had to comment out an instruction (PUSHES) which overlapped the 0x06 opcode. This was OK in my case (as far as I know) because PUSHES isn't implemented in gem5. Thanks again! Gus On Sun, Mar 18, 2018 at 11:30 PM, Craig Topper <craig.topper at gmail.com> wrote: > ASM is the text output you want printed in a textual listing of the > assembly. The curly b...

...command line option to change this behavior. You can then get a meaningful backtrace from your debugger if you break on the gdk_x_error() function.) Konqueror doesn't crash but doesn't display the image and print : X Error: BadAlloc (insufficient resources for operation) 11 Major opcode: 53 Minor opcode: 0 Resource id: 0x26003c3 X Error: BadDrawable (invalid Pixmap or Window parameter) 9 Major opcode: 72 Minor opcode: 0 Resource id: 0x26003c3 X Error: BadDrawable (invalid Pixmap or Window parameter) 9 Major opcode: 72 Minor opcode: 0 Resource id: 0x26003c...

This set is part of a larger effort attempting to clean-up W=1 kernel builds, which are currently overwhelmingly riddled with niggly little warnings. Lee Jones (15): drm/xlnx/zynqmp_disp: Use correct kerneldoc formatting in zynqmp_disp drm/xlnx/zynqmp_dp: Fix function name zynqmp_dp_link_train() -> zynqmp_dp_train() drm/vkms/vkms_composer: Fix a few different kerneldoc formatting

________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Friday, September 19, 2008 10:49 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Custom Opcodes versus built-in opcodes On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've...

On Thu, Sep 18, 2008 at 4:04 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I am using lowering instructions and using custom opcodes that I can more > easily directly map to my backend. These opcodes are then used to emit a > custom set of instructions into the MachineBasicBlock. I've been able to get > one to work correctly, however, I've ran into an issue where my second one > is being confused as a FRAME...

This set is part of a larger effort attempting to clean-up W=1 kernel builds, which are currently overwhelmingly riddled with niggly little warnings. Cc: Alex Deucher <alexander.deucher at amd.com> Cc: amd-gfx at lists.freedesktop.org Cc: Ben Skeggs <bskeggs at redhat.com> Cc: "Christian K?nig" <christian.koenig at amd.com> Cc: Daniel Vetter <daniel at ffwll.ch>

...uction [root at sip32 admin]# [root at sip32 admin]# /usr/sbin/asterisk -c Illegal instruction Why can I not start Asterisk ? I also notice the following in /var/log/asterisk : [root at sip32 admin-voipcenter]# tail -f /var/log/messages Nov 20 14:04:31 sip32 kernel: asterisk[2034] trap invalid opcode ip:530b18 sp:7fffa6051a60 error:0 in asterisk[400000+1d7000] Nov 20 14:04:31 sip32 kernel: asterisk[2034] trap invalid opcode ip:530b18 sp:7fffa6051a60 error:0 in asterisk[400000+1d7000] Nov 20 14:04:35 sip32 kernel: asterisk[2041] trap invalid opcode ip:530b18 sp:7fff11d96bf0 error:0 in asteri...

Hello, The LLVM IR opcodes Add, Sub, and Mul have been each split into two. Add, Sub, and Mul now only handle integer types, and three new opcodes, FAdd, FSub, and FMul now handle floating-point types. The main LLVM APIs are currently preserving backwards compatibility, transparently mapping integer opcodes to correspond...

On Sep 19, 2008, at 11:35 AM, Villmow, Micah wrote: > Make sure to use DAG.getTargetNode() with custom opcodes. "target" > nodes are encoded with an implicit delta added to their enum value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their lowering functions with...

...r, the VGA BIOS or an on-board small microcontroller which provides certain security assertions (the 'PMU'). This system allows a GPU programming sequence to be shared by multiple entities that would not otherwise be able to execute common code. This series adds support to nouveau for two opcodes seen on VBIOSes prior to the locked-down PMU taking over responsibility for executing devinit scripts. Documentation for these two opcodes can be found at: https://github.com/envytools/envytools/pull/189 Rhys Kidd (2): drm/nouveau/bios/init: handle INIT_RESET_BEGUN devinit opcode drm/nou...

https://bugs.freedesktop.org/show_bug.cgi?id=57837 Priority: medium Bug ID: 57837 Assignee: nouveau at lists.freedesktop.org Summary: nouveau invalid opcode for NVIDIA QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: All Reporter: yetist at gmail.com Hardware: Other Status: NEW Version: unspecified Component: Driver/nouveau...

tl;dr, I'd like to add my own instruction, but I'm running into problems due to my lack of x86 encoding/decoding understanding. Hello all. Currently, I'm working on adding my own x86 instruction. I have done this once before; the basic process I used was: 1. Find an unused opcode, e.g. 0xF1 in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into lib/Target/X86/X86InstrInfo.td using this opcode. In this case, I used 0xF1, and created the following instruction: def CACHE_OPERAND_B64i : RIi64<0xF1, AddRegFrm, (outs GR64:$unused),...