Displaying 7 results from an estimated 7 matches for "opc_recordnode".
2014 Nov 05
2
[LLVMdev] Virtual register def doesn't dominate all uses
...Vrr instruction. This is likely the problem.
> Do you know how to debug this, or do you want me to give you basic directions?
I had a look at the matcher table and it looks as follows:
/*4309*/ /*Scope*/ 12, /*->4322*/
/*4310*/ OPC_CheckOpcode, TARGET_VAL(MBPISD::RET_FLAG),
/*4313*/ OPC_RecordNode, // #0 = 'retflag' chained node
/*4314*/ OPC_CaptureGlueInput,
/*4315*/ OPC_EmitMergeInputChains1_0,
/*4316*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::RETL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0,
0/*#VTs*/, 0/*#Ops*/,
// Src: (retflag) - Complexity...
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
Hello.
I come back to this older thread.
Again, because of i64immSExt32 I receive TableGen error "Could not infer all types
in, pattern!" (exact details written below). So far I'm not able to generate selection
code with TableGen for the ADD_r* instructions, etc:
def i64immSExt32 : PatLeaf<(imm),
[{return
2014 Nov 03
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
>> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same.
>
> And what about view-sched-dags?
The DAG looks like I described below (*)
> This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection
2016 Jun 22
2
LLVM Backend Issues
Thanks Anton and Krzysztof!
Here is the dump using the -debug flag. At this point I am not making much
sense of this, would it be too much to ask if one of you could walk me
through one of these lines?
One thing that I didn't point out is that I never defined any separate
floating point registers, not sure if this will pose any issue?
Thanks again for your time!
Jeff
jeff at
2014 Mar 08
2
[LLVMdev] Isel DAG documentation?
On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote:
> ISDOpcodes.h contains what documentation there is on the semantics of each
> opcode.
And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in
MachineInstr form, but you'll see them with -view-sched-dags, and
occasionally before).
Tim.
2014 Mar 09
2
[LLVMdev] Isel DAG documentation?
...d to create a cycle in the DAG, which is
> of course wrong. But how?
When I write a similar pattern into the ARM .td files and look at
(from the build directory) lib/Target/ARM/ARMGenDAGISel.inc, I see:
/*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494
/*56481*/ OPC_RecordNode, // #0 = $src
/*56482*/ OPC_CheckType, MVT::i32,
/*56484*/ OPC_CheckPatternPredicate, 4, // (!Subtarget->isThumb())
/*56486*/ OPC_MorphNodeTo, TARGET_VAL(ARM::MOVi32imm), 0,
1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
// Src: (globaladdr:i32):$src - Complexity...
2016 Feb 04
2
llc gives Segmentation fault at instruction selection [was Re: Instruction selection gives "LLVM ERROR: Cannot select"]
Hello, Tim,
Thank you for your advice.
Indeed, the problem with "LLVM ERROR: Cannot select" was a false predicate that
should have been true. I solved the problem by simply making the C++ function implementing
the TableGen predicate used in my store instruction (very similar to the selectIntAddrMSA
predicate from the Mips back end) return true instead of false.
But