Displaying 10 results from an estimated 10 matches for "opc_movepar".
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
.../*2235*/ OPC_SwitchOpcode /*2 cases */, 27,
> TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266
> /*2239*/ OPC_RecordChild0, // #1 = $addr
> /*2240*/ OPC_MoveChild, 0,
> /*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress),
> /*2245*/ OPC_MoveParent,
> /*2246*/ OPC_MoveParent,
> /*2247*/ OPC_CheckPredicate, 5, // Predicate_unindexedload
> /*2249*/ OPC_CheckPredicate, 6, // Predicate_load
> /*2251*/ OPC_CheckType, MVT::i64,
> /*2253*/ OPC_EmitMergeInputChains1_0,
> /*2254*/...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
In an attempt to add vector registers to my target, I ran into a problem.
LLVM started to complain about not being able to infer types from the
provided DAG patterns for several classes of instructions. After a
discussion on the llvm-dev mailing list and IRC channel the recommendation
was to make DAG patterns for these classes of instructions more specific.
Which is what was done. However after
2012 Mar 14
2
[LLVMdev] Data/Address registers
...located at different scopes. For these two
patterns, tblgen is producing the following isel opcodes:
/*3244*/ /*Scope*/ 20, /*->3265*/
/*3245*/ OPC_RecordChild1, // #1 = $b
/*3246*/ OPC_MoveChild, 1,
/*3248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/*3251*/ OPC_MoveParent,
/*3252*/ OPC_CheckType, MVT::i16,
/*3254*/ OPC_EmitConvertToTarget, 1,
/*3256*/ OPC_MorphNodeTo, TARGET_VAL(ME::AADDMri), 0,
and in the same logic chain of pattern checking, DADDri comes right
after AADDMri (with Scope changes in the middle)
/*3285*/ OPC_RecordChild...
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...pcode, TARGET_VAL(ISD::SIGN_EXTEND),
/* 3*/ OPC_MoveChild0,
/* 4*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
/* 7*/ OPC_MoveChild0,
/* 8*/ OPC_CheckOpcode, TARGET_VAL(ISD::ANY_EXTEND),
/* 11*/ OPC_RecordChild0, // #0 = $src
/* 12*/ OPC_CheckChild0Type, MVT::i16,
/* 14*/ OPC_MoveParent,
/* 15*/ OPC_RecordChild1, // #1 = $imm
/* 16*/ OPC_MoveChild1,
/* 17*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/* 20*/ OPC_CheckPredicate, 0, // Predicate_Imm_17_31_i16
/* 22*/ OPC_CheckType, MVT::i16,
/* 24*/ OPC_MoveParent,
/* 25*/ OPC_CheckType, MVT::i32,
/*...
2012 Mar 14
0
[LLVMdev] Data/Address registers
...For these two patterns, tblgen is producing the following isel opcodes:
>
> /*3244*/ /*Scope*/ 20, /*->3265*/
> /*3245*/ OPC_RecordChild1, // #1 = $b
> /*3246*/ OPC_MoveChild, 1,
> /*3248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
> /*3251*/ OPC_MoveParent,
> /*3252*/ OPC_CheckType, MVT::i16,
> /*3254*/ OPC_EmitConvertToTarget, 1,
> /*3256*/ OPC_MorphNodeTo, TARGET_VAL(ME::AADDMri), 0,
>
> and in the same logic chain of pattern checking, DADDri comes right after AADDMri (with Scope changes in the middle)
>...
2012 Mar 07
0
[LLVMdev] Data/Address registers
On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi Jim,
>
> Thanks for your response.
>
> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>> Hi Ivan,
>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I'm facing a problem in llvm while porting it
2012 Mar 07
2
[LLVMdev] Data/Address registers
Hi Jim,
Thanks for your response.
Le 06/03/2012 22:54, Jim Grosbach a écrit :
> Hi Ivan,
> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi,
>>
>> I'm facing a problem in llvm while porting it to a new target and I'll
>> need some support.
>> We have 2 kind of register, one for general purposes (i.e.
2016 Feb 22
2
Failure to match a DAG after a minor pattern change in a custom Target
...> /*38*/ OPC_MoveChild, 1,
> /*40*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
> /*43*/ OPC_Scope, 65, /*->110*/ // 7 children in Scope
> /*45*/ OPC_CheckPredicate, 0, // Predicate_u32ImmPred
> /*47*/ OPC_MoveParent,
> /*48*/ OPC_CheckType, MVT::i32,
>
> When the matcher says "false predicate at index 123", you can look at the
> line marked with /*123*/ and see exactly what predicate it was checking.
> This helps immensely with solving such problems.
>
>
>...
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
Hello.
I come back to this older thread.
Again, because of i64immSExt32 I receive TableGen error "Could not infer all types
in, pattern!" (exact details written below). So far I'm not able to generate selection
code with TableGen for the ADD_r* instructions, etc:
def i64immSExt32 : PatLeaf<(imm),
[{return