Displaying 7 results from an estimated 7 matches for "opc_emitnode".
Did you mean:
opc_emitnode1
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
...to modify the above pattern where in the LDriw (the second load in the
COMBINE_rr) is changed to LDriw_indexed similar to the first load.
I see the following in HexagonGenDAGISel.inc
***********************************************
/*1161*/ OPC_EmitConvertToTarget, 2,
/*1163*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
0|OPFL_Chain,
1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 6, // Results =
#7
/*1172*/ OPC_EmitConvertToTarget, 5,
/*1174*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
0|OPFL_Chain,
1/*#VTs*/...
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
Hi,
On the hexagon target, I have written a following combiner pattern.
*********************************************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 2:57 PM, Phil Tomson wrote:
>
>
> I see the following in my SelectCode (in XSTGGenDGISel.inc):
>
>
> /*2235*/ OPC_SwitchOpcode /*2 cases */, 27,
> TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266
> /*2239*/ OPC_RecordChild0, // #1 = $addr
> /*2240*/ OPC_MoveChild, 0,
> /*2242*/ OPC_CheckOpcode,
2012 Mar 14
2
[LLVMdev] Data/Address registers
...#0 = $a
/*3286*/ OPC_RecordChild1, // #1 = $b
/*3287*/ OPC_Scope, 42, /*->3331*/ // 2 children in Scope
/*3289*/ OPC_MoveChild, 1,
/*3291*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/*3294*/ OPC_MoveParent,
/*3295*/ OPC_CheckType, MVT::i16,
/*3297*/ OPC_EmitNode, TARGET_VAL(ME::sextr), 0,
1/*#VTs*/, MVT::i64, 1/*#Ops*/, 0, // Results = #2
/*3305*/ OPC_EmitConvertToTarget, 1,
/*3307*/ OPC_EmitNodeXForm, 0, 3, // XLoadImm
...
AADDMri supersedes DADDri (the same checks are performed). It's worth to
note that the resul...
2012 Mar 14
0
[LLVMdev] Data/Address registers
...rdChild1, // #1 = $b
> /*3287*/ OPC_Scope, 42, /*->3331*/ // 2 children in Scope
> /*3289*/ OPC_MoveChild, 1,
> /*3291*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
> /*3294*/ OPC_MoveParent,
> /*3295*/ OPC_CheckType, MVT::i16,
> /*3297*/ OPC_EmitNode, TARGET_VAL(ME::sextr), 0,
> 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 0, // Results = #2
> /*3305*/ OPC_EmitConvertToTarget, 1,
Huh. I would have expected OPC_EmitRegister here. Probably something different in your target causing this. I don't anticipate that it'll c...
2012 Mar 07
0
[LLVMdev] Data/Address registers
On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi Jim,
>
> Thanks for your response.
>
> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>> Hi Ivan,
>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I'm facing a problem in llvm while porting it
2012 Mar 07
2
[LLVMdev] Data/Address registers
Hi Jim,
Thanks for your response.
Le 06/03/2012 22:54, Jim Grosbach a écrit :
> Hi Ivan,
> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi,
>>
>> I'm facing a problem in llvm while porting it to a new target and I'll
>> need some support.
>> We have 2 kind of register, one for general purposes (i.e.