Displaying 3 results from an estimated 3 matches for "opc_emitinteger".
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...t,
/* 28*/ OPC_CheckType, MVT::i40,
/* 30*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
MVT::i40, 0/*#Ops*/, // Results = #2
/* 36*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
MVT::i32, 0/*#Ops*/, // Results = #3
/* 42*/ OPC_EmitInteger, MVT::i32, OurTarget::hi16, // Results = #4
/* 45*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
MVT::i32, 3/*#Ops*/, 3, 0, 4, // Results = #5
/* 54*/ OPC_EmitNode1, TARGET_VAL(OurTarget::clearLo32_pseudo), 0,
MVT::i32, 1/*#Ops*/, 5, // Result...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...> /*2246*/ OPC_MoveParent,
> /*2247*/ OPC_CheckPredicate, 5, // Predicate_unindexedload
> /*2249*/ OPC_CheckPredicate, 6, // Predicate_load
> /*2251*/ OPC_CheckType, MVT::i64,
> /*2253*/ OPC_EmitMergeInputChains1_0,
> /*2254*/ OPC_EmitInteger, MVT::i64, 0,
> /*2257*/ OPC_MorphNodeTo, TARGET_VAL(XSTG::LOADI64_RI),
> 0|OPFL_Chain|OPFL_MemRefs,
> 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,
> // Src: (ld:i64 (XSTGADDR_NORMAL:iPTR
> (tglobaladdr:iPTR):$addr))<<P:Predicate_unin...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI