Displaying 8 results from an estimated 8 matches for "opc_emitconverttotarget".
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
...>;
> ******************************
I had to modify the above pattern where in the LDriw (the second load in the
COMBINE_rr) is changed to LDriw_indexed similar to the first load.
I see the following in HexagonGenDAGISel.inc
***********************************************
/*1161*/ OPC_EmitConvertToTarget, 2,
/*1163*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
0|OPFL_Chain,
1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 6, // Results =
#7
/*1172*/ OPC_EmitConvertToTarget, 5,
/*1174*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed),
0|OPFL_Cha...
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
Hi,
On the hexagon target, I have written a following combiner pattern.
*********************************************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr
2012 Mar 14
2
[LLVMdev] Data/Address registers
...the following isel opcodes:
/*3244*/ /*Scope*/ 20, /*->3265*/
/*3245*/ OPC_RecordChild1, // #1 = $b
/*3246*/ OPC_MoveChild, 1,
/*3248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/*3251*/ OPC_MoveParent,
/*3252*/ OPC_CheckType, MVT::i16,
/*3254*/ OPC_EmitConvertToTarget, 1,
/*3256*/ OPC_MorphNodeTo, TARGET_VAL(ME::AADDMri), 0,
and in the same logic chain of pattern checking, DADDri comes right
after AADDMri (with Scope changes in the middle)
/*3285*/ OPC_RecordChild0, // #0 = $a
/*3286*/ OPC_RecordChild1, // #1 = $b
/*3287*/ OPC_Scope, 42,...
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
In an attempt to add vector registers to my target, I ran into a problem.
LLVM started to complain about not being able to infer types from the
provided DAG patterns for several classes of instructions. After a
discussion on the llvm-dev mailing list and IRC channel the recommendation
was to make DAG patterns for these classes of instructions more specific.
Which is what was done. However after
2012 Mar 14
0
[LLVMdev] Data/Address registers
.../*3244*/ /*Scope*/ 20, /*->3265*/
> /*3245*/ OPC_RecordChild1, // #1 = $b
> /*3246*/ OPC_MoveChild, 1,
> /*3248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
> /*3251*/ OPC_MoveParent,
> /*3252*/ OPC_CheckType, MVT::i16,
> /*3254*/ OPC_EmitConvertToTarget, 1,
> /*3256*/ OPC_MorphNodeTo, TARGET_VAL(ME::AADDMri), 0,
>
> and in the same logic chain of pattern checking, DADDri comes right after AADDMri (with Scope changes in the middle)
>
> /*3285*/ OPC_RecordChild0, // #0 = $a
> /*3286*/ OPC_RecordChild1, // #1 = $b...
2012 Mar 07
0
[LLVMdev] Data/Address registers
On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi Jim,
>
> Thanks for your response.
>
> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>> Hi Ivan,
>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I'm facing a problem in llvm while porting it
2012 Mar 07
2
[LLVMdev] Data/Address registers
Hi Jim,
Thanks for your response.
Le 06/03/2012 22:54, Jim Grosbach a écrit :
> Hi Ivan,
> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi,
>>
>> I'm facing a problem in llvm while porting it to a new target and I'll
>> need some support.
>> We have 2 kind of register, one for general purposes (i.e.
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
Hello.
I come back to this older thread.
Again, because of i64immSExt32 I receive TableGen error "Could not infer all types
in, pattern!" (exact details written below). So far I'm not able to generate selection
code with TableGen for the ADD_r* instructions, etc:
def i64immSExt32 : PatLeaf<(imm),
[{return