search for: opc_checkpredicate

Displaying 8 results from an estimated 8 matches for "opc_checkpredicate".

2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...OPC_RecordChild0, // #1 = $addr > /*2240*/ OPC_MoveChild, 0, > /*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress), > /*2245*/ OPC_MoveParent, > /*2246*/ OPC_MoveParent, > /*2247*/ OPC_CheckPredicate, 5, // Predicate_unindexedload > /*2249*/ OPC_CheckPredicate, 6, // Predicate_load > /*2251*/ OPC_CheckType, MVT::i64, > /*2253*/ OPC_EmitMergeInputChains1_0, > /*2254*/ OPC_EmitInteger, MVT::i64, 0, &gt...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote: > > Ah, I see, the defm is a multi-class so I needed to change it to: > > def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)), > (LOADI64_RI tglobaladdr:$addr, 0)>; > // Match load from a relocatable address to a load with GRP: > def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)), >
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
In an attempt to add vector registers to my target, I ran into a problem. LLVM started to complain about not being able to infer types from the provided DAG patterns for several classes of instructions. After a discussion on the llvm-dev mailing list and IRC channel the recommendation was to make DAG patterns for these classes of instructions more specific. Which is what was done. However after
2017 Aug 15
3
How to debug instruction selection
Hi there, I try to JIT compile some bitcode and seeing the following error: LLVM ERROR: Cannot select: 0x28ec830: ch,glue = X86ISD::CALL 0x28ec7c0, 0x28ef900, Register:i32 %EDI, Register:i8 %AL, RegisterMask:Untyped, 0x28ec7c0:1 0x28ef900: i32 = X86ISD::Wrapper TargetGlobalAddress:i32<void (i8*, ...)* @_ZN5FooBr7xprintfEPKcz> 0 0x28ec520: i32 = TargetGlobalAddress<void (i8*, ...)*
2016 Feb 22
2
Failure to match a DAG after a minor pattern change in a custom Target
...ld1, // #3 = $offset > /*38*/ OPC_MoveChild, 1, > /*40*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant), > /*43*/ OPC_Scope, 65, /*->110*/ // 7 children in Scope > /*45*/ OPC_CheckPredicate, 0, // Predicate_u32ImmPred > /*47*/ OPC_MoveParent, > /*48*/ OPC_CheckType, MVT::i32, > > When the matcher says "false predicate at index 123", you can look at the > line marked with /*123*/ and see exactly...
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return
2016 Jun 22
2
LLVM Backend Issues
Thanks Anton and Krzysztof! Here is the dump using the -debug flag. At this point I am not making much sense of this, would it be too much to ask if one of you could walk me through one of these lines? One thing that I didn't point out is that I never defined any separate floating point registers, not sure if this will pose any issue? Thanks again for your time! Jeff jeff at
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...ecordChild0, // #0 = $src /* 12*/ OPC_CheckChild0Type, MVT::i16, /* 14*/ OPC_MoveParent, /* 15*/ OPC_RecordChild1, // #1 = $imm /* 16*/ OPC_MoveChild1, /* 17*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant), /* 20*/ OPC_CheckPredicate, 0, // Predicate_Imm_17_31_i16 /* 22*/ OPC_CheckType, MVT::i16, /* 24*/ OPC_MoveParent, /* 25*/ OPC_CheckType, MVT::i32, /* 27*/ OPC_MoveParent, /* 28*/ OPC_CheckType, MVT::i40, /* 30*/ OPC_EmitNode1, TARGET_VAL(TargetO...