Displaying 4 results from an estimated 4 matches for "opc0".
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gpc0
2009 Jul 02
1
[LLVMdev] [Help Needed] tblgen code get a compile error
...39; :
cannot convert parameter 6 from 'llvm::SDValue' to 'const llvm::SDValue *'
No user-defined-conversion operator available that can perform this
conv
ersion, or the operator cannot be called
I checked the generated the code:
SDNode *Emit_2(const SDValue &N, unsigned Opc0, MVT VT0) DISABLE_INLINE {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i8,
MVT::Flag, N0, N1); <==== error here.
SDValue InFlag(ResNode, 2);
ReplaceUses(SDValue(N.getNode(), 1), InFlag);
return Res...
2006 Aug 09
2
[LLVMdev] Tablegen problem in LLVM 1.8
...he NOINLINE-macro after each method's argument list and right before
the "{" in the various lib/Target/XXX/XXXGenDAGISel.inc-files seems to
be the culprit, e.g. in llvm-build/lib/Target/ARM/ARMGenDAGISel.inc
(line 145):
void Emit_0(SDOperand &Result, SDOperand &N, unsigned Opc0, SDOperand
&Chain, SDOperand &N1, bool HasInFlag) NOINLINE {
...
If I remove all NOINLINE appearances, everything compiles although I get
47 unexpected failures upon lib/test-ing (test results in attachment). I
didn't have these compilation problems with 1.7, although I remember...
2008 Oct 20
2
[LLVMdev] TableGen Hacking Help
...to handle more complex things or tblgen needs to emit
ReplaceUses after it generates the two MOVSD instructions. Perhaps something
like this:
SDOperand Ops0[] = { CPTmp0001, CPTmp1001, CPTmp2001, CPTmp3001,
LSI_N00_Child0, LSI_N10_Child0, Chain10 };
SDOperand Tmp1(CurDAG->getTargetNode(Opc0, VT0, MVT::Other, Ops0, 7), 0);
ReplaceUses(SDOperand(N00.Val, 0), Tmp1);
I don't know if the parameters to that ReplaceUses call are correct, but I
think you'll get the idea.
The problem of course is that other patterns cause this kind of recursion to
match their memory operands and...
2010 Feb 22
4
[LLVMdev] SelectionDAG legality: isel creating cycles
...3b610: i64 = undef
I added the brackets on output to show which result is being linked to, so the
prefetch takes the chain output from its controlling load.
When llvm.x86.sse2.min.sd gets selected, the TableGen-generated code
does this:
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other,
Ops0, 6);
0x215f140: v2f64,ch = <<Unknown Machine Node>> 0x21606d0, 0x213ac00,
0x215ffa0, 0x215ea10, 0x215ee60, 0x213a720
[0] 0x21606d0: v2f64 = scalar_to_vector 0x213b8f0
[0] 0x213b8f0: f64,ch = load 0x213b780, 0x213aa90, 0x213b610 <0x2113690:0>
alignment=...