search for: opc

Hello! I have some questions about Wine and how/if it can be used with industrial communication like OPC (MicroSoft Com/DCom objects, DDE and more) My short question is: Can I use Wine to make OPC communication work with a Linux system. OPC "OLE for Process Control" A "general" standard for communication in industrial systems, that unfortunately is totally depending on Windows...

...---------------------------------- System info: R version rw1020 on NT ESS using emacs ver. 20.4 ---------------------------------- To keep my scripts short and tidy, I want to call sub-functions and return variables from these for subsequent use in the calling function. e.g. "test.smooth.opc.time.series" <- function() { load.opc.ascii.files() } Within the sub-function "load.opc.ascii.files" I have tried two ways of assigning variables for use by the calling function "test.smooth.opc.time.series": dir <<- c('h:/data/nov99_tan991...

...00000020000000 (Reserved) (XEN) HVM10: (XEN) HVM10: Start BIOS ... (XEN) HVM10: Starting emulated 16-bit real-mode: ip=F000:FFF0 (XEN) HVM10: 0x000FFFF0: 0xF000:0xFFF0 (0) <VM86_REAL> (XEN) HVM10: rombios.c,v 1.138 2005/05/07 15:55:26 vruppert Exp $ (XEN) HVM10: 0x000FE260: 0xF000:0xE260 (0) opc 0xB0 (XEN) HVM10: Remapping master: ICW2 0x8 -> 0x20 (XEN) HVM10: 0x000FE264: 0xF000:0xE264 (0) opc 0xB0 (XEN) HVM10: Remapping slave: ICW2 0x70 -> 0x28 (XEN) HVM10: 0x000FE268: 0xF000:0xE268 (0) opc 0xB0 (XEN) HVM10: 0x000FE26C: 0xF000:0xE26C (0) opc 0xB0 (XEN) HVM10: 0x000FE270: 0xF000:0xE2...

Is it legal to do something like a !strconcat on a non-string entity? That is, is there some operation that will let me do this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // Vector operation emulating scalar (fp) def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32: $src2), !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, $src2}"),...

...Yeah, exactly those 2 things. I have them in separate patches, but I think we only get the benefit from sized binary literals if we also allow them to initialize multiple bits in another bits<n> type. Thanks, Pete > I.e. I don’t think we currently accept: > > bits<4> x = { opc, opc } > > Thanks, > Adam -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140730/6b7396ac/attachment.html>

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc, "", (outs), (ins), [(int_no_operand)]>; *InstrFormat.td* multiclass Clr { def _ : ALU<&qu...

Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya

...point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } class ALU<string opc> : TestInst<opc, "", (outs), (ins)>; See if you get the same error. I suspect it has to do with the intrinsic itself, not the instruction d...

...ts, I think they expect to get a value with 3 bits, and not a 2-bit value which is silently truncated and later silently zero extended. Given this, I would then like to extend bits initializers to accept these new sized binary literals. For example, I would like to be able to write bits<2> opc; bits<8> x = { opc, 0b1100, rd{1}, rs{0} } This would let us write some encodings much more concisely, instead of having to put each initializer on its own line. I do have patches, which I’m happy to present for review, but I’d like some feedback on the general idea before we get to the low...

...experience in this area, hope you don't mind. > assume I use LabView on Windows to make a standalone .exe > this .exe communicates with the EIB fieldbus using a bus coupler unit > that communicates with a normal serial interface COM (9600bps). > > Under windows LabView uses the OPC server to provide an interface with > the EIB bus. > > Do you think it would be possible to run the standalone .exe on Linux + > wine with > the bus coupler attached to the serial port ? It's possible, I'm sure. The question is how much work it will take. Rarely do thin...

..., is there some operation that will let me do this (replace > SOME_CONCAT with > an appropriate operator): I don't get it, can you try a simpler example on me? :) -Chris > > > (WARNING! Hacked-up tablegen ahead!) > > multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, > SDNode OpNode> { > // Vector operation emulating scalar (fp) > def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, > FR32: > $src2), > !strconcat(OpcodeStr, "ps"\t{$src...

...gt; SelectionDAG &DAG) const { > SDValue LHS = Op.getOperand(0); > SDValue RHS = Op.getOperand(1); > SDValue TrueVal = Op.getOperand(2); > SDValue FalseVal = Op.getOperand(3); > DebugLoc dl = Op.getDebugLoc(); > unsigned Opc; > > SDValue CompareFlag; > if (LHS.getValueType() == MVT::i32) { > Opc = MBlazeISD::Select_CC; > CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS) > .getValue(1); > } else { > llvm_unreachable("Cannot lower select_...

...of ESP immediately before this instruction, + // merge the two. This can be the case when tail call elimination is + // enabled and the callee has more arguments then the caller + if (MBBI != MBB.begin()) { + MachineBasicBlock::iterator PI = prior(MBBI); + unsigned Opc = PI->getOpcode(); + if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || + Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && Weird indentation? +/// CheckAndDeletePreceedingADD - looks at instruction before the passed +/// instruction if it is an ADD instruc...

...avx_fp_cvt_scalar_xs_scalar64_xs_node_sintrinsic_rm< 0x2D, "cvtsi2ss", sint_to_fp, "cvtsi2ss", "f32", "i32">; [Meanwhile, down in the guts...] class fp_cvt_scalar_VXSnrr< // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr bits<8> opc, string OpcodeStr, SDNode OpNode, string DstType, string SrcType, int CustomPatterns = 0, list<dag> patterns = [], string asm = "" >: fp_unary_vxs_n_rm_rr< opc, !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",!patsubst("^...

...R || > + ldst->src(0).getFile() == FILE_MEMORY_GLOBAL) && > ldst->src(0).isIndirect(0) && > ldst->getIndirect(0, 0)->reg.size == 8; > } > @@ -1779,8 +1781,13 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i) > uint32_t opc; > > switch (i->src(0).getFile()) { > - case FILE_MEMORY_BUFFER: opc = 0x90000000; break; > - case FILE_MEMORY_LOCAL: opc = 0xc8000000; break; > + case FILE_MEMORY_BUFFER: > + case FILE_MEMORY_GLOBAL: > + opc = 0x90000000; > + break; > + case...

..._xs_node_sintrinsic_rm< > 0x2D, "cvtsi2ss", sint_to_fp, "cvtsi2ss", "f32", "i32">; > > [Meanwhile, down in the guts...] > > class fp_cvt_scalar_VXSnrr< > // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr > bits<8> opc, > string OpcodeStr, > SDNode OpNode, > string DstType, > string SrcType, > int CustomPatterns = 0, > list<dag> patterns = [], > string asm = "" >> : fp_unary_vxs_n_rm_rr< > opc, > !cast<RegisterClass>(!patsubst("^f([0-9]+)...

Hi all, I changed the code that checks whether a tail call is really eligible for optimization so that it performs the check/fix in SelectionDAGISel.cpp:BuildSelectionDAG() as suggest by Evan. Also eliminated an error that caused the remaining failing test cases in the test-suite. The results look very nice (on darwin x86, r42486). The same number (46) of failing test cases on patched

...sing xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass *rc ) const { unsigned Opc; if (rc == &X86::GR32RegClass) { Opc = X86::XCHG32rr; } else if (rc == &X86::GR16RegClass) { Opc = X86::XCHG16rr; } else if (rc == &X86::GR8RegClass) { Opc = X86::XCHG8rr; } else { assert(0 && "Unknown regclass in add...

...egister > classes. > Please look at the documentation for "multiclass" and "defm". In the X86InstrSSE.td file, we have this, which looks very similar to what you have above. let Constraints = "$src1 = $dst" in { multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, bit Commutable = 0> { // Scalar operation, reg+reg. def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strconcat(OpcodeStr,...

________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Friday, September 19, 2008 10:49 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Custom Opcodes versus built-in opcodes On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I'...