Displaying 8 results from an estimated 8 matches for "op_union".
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2014 May 13
1
[PATCH 1/2] nv50/ir: make sure that texprep/texquerylod's args get coalesced
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.2" <mesa-stable at lists.freedesktop.org>
---
Not 100% sure of the significance of this code, but this seems like the
correct thing to do... will definitely run it through a full piglit run before
pushing out.
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...i);
+ ValueDef &def2 = su2d->def(i);
+ Instruction *mov = NULL;
+
+ if (pred) {
+ mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
+ mov->setPredicate(CC_P, pred->getDef(0));
+ }
+
+ Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
+ bld.getSSA(),
+ NULL, def2.get());
+ def.replace(uni->getDef(0), false);
+ uni->setSrc(0, def.get());
+ if (mov)
+ uni->setSrc(2, mov->getDef(0));
+ }
+ } els...
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
...(int j = 0; j < 5; ++j)
r[j] = bld->getSSA(fullSize);
i[8] = bld->mkOp2(OP_SHR, fTy, r[0], t[1], bld->mkImm(halfSize * 8));
i[6] = bld->mkOp2(OP_ADD, fTy, r[1], r[0], imm);
bld->mkMov(r[3], r[0])->setPredicate(CC_NC, c[0]);
bld->mkOp2(OP_UNION, TYPE_U32, r[2], r[1], r[3]);
- i[5] = bld->mkOp3(OP_MAD, fTy, mul->getDef(0), a[1], b[1], r[2]);
+ i[5] = bld->mkOp3(OP_MAD, fTy, r[4], a[1], b[1], r[2]);
// set carry defs / sources
i[3]->setFlagsDef(1, c[0]);
- i[4]->setFlagsDef(0, c[1]); // actual r...
2017 Jul 31
1
[RFC PATCH] nv50/ir: allow spilling of def values for constrained MERGES/UNIONS
...@@ -2344,8 +2344,6 @@ RegAlloc::InsertConstraintsPass::insertConstraintMoves()
cst->setSrc(s, mov->getDef(0));
cst->bb->insertBefore(cst, mov);
- cst->getDef(0)->asLValue()->noSpill = 1; // doesn't help
-
if (cst->op == OP_UNION)
mov->setPredicate(defi->cc, defi->getPredicate());
}
--
2.13.3
2014 Aug 30
2
[PATCH 1/2] nvc0/ir: avoid infinite recursion when finding first uses of tex
...+ * merging. This should probably be moved to being done right before
+ * RA. But this will do for now.
+ */
+ if (visited.find(usei) != visited.end())
+ continue;
+
+ visited.insert(usei);
+
if (usei->op == OP_PHI || usei->op == OP_UNION) {
// need a barrier before WAW cases
for (int s = 0; usei->srcExists(s); ++s) {
@@ -197,11 +213,11 @@ NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
usei->op == OP_PHI ||
usei->op == OP_UNION) {
// these uses d...
2014 Dec 02
0
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
...n->getSrc(0)))
- insn = insn->getSrc(0)->getUniqueInsn();
+ insn = insn->getSrc(0)->getUniqueInsnMerged();
if (!insn->bb->reachableBy(texi->bb, term))
return;
@@ -163,7 +163,7 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
case OP_UNION:
/* recurse again */
for (int s = 0; insn->srcExists(s); ++s)
- findOverwritingDefs(texi, insn->getSrc(s)->getUniqueInsn(), term,
+ findOverwritingDefs(texi, insn->getSrc(s)->getUniqueInsnMerged(), term,
uses);
break;...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...1))
+ ->setFlagsDef(0, pred);
+ shr[2] = bld.getSSA(4); shr[3] = bld.getSSA(4);
+ bld.mkOp2(OP_OR, TYPE_U32, shr[2], shr[0], bld.loadImm(NULL, 0x80000000))
+ ->setPredicate(CC_S, pred);
+ bld.mkMov(shr[3], shr[0])
+ ->setPredicate(CC_NS, pred);
+ shr[0] = bld.mkOp2v(OP_UNION, TYPE_U32, bld.getSSA(4), shr[2], shr[3]);
+
+ guess = bld.mkOp2v(OP_SUB, TYPE_F64, bld.getSSA(8), guess,
+ bld.mkOp2v(OP_MERGE, TYPE_F64, bld.getSSA(8), shr[0], shr[1]));
+
+ if (i->op == OP_RCP) {
+ Value *two = bld.getSSA(8), *neg = bld.getSSA(8), *copy = bld.get...
2014 Jul 18
5
[PATCH 0/5] nvc0: fp64 preparation
Most of codegen is already FP64-ready. There are a few edge-cases that I ran
into, many of which can apply even to non-fp64-enabled programs (although the
double-wide registers are not very common without fp64).
I've yet to give this a full piglit run, but wanted to send these out in case
someone wanted to comment. They do not depend on the preliminary core fp64
work.
Ilia Mirkin (5):