Displaying 6 results from an estimated 6 matches for "op_suffix".
2011 Oct 06
4
[LLVMdev] TableGen and Greenspun
..."pasting" operation but I've found it
to be too limiting. In this example:
(Equivalent TableGen code with a for-loop)
----------------------------------------
multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
for nbit = [32, 32, 64, 64],
op_suffix = [r, i, r, i],
op_type = [RegF32, f32imm, RegF64, f64imm],
op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
def rr#op_suffix#nbit
: InstPTX<(outs RegF#nbit:$d),
(ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c),
!strconcat(opcstr, &quo...
2011 Oct 06
0
[LLVMdev] TableGen and Greenspun
Jakob Stoklund Olesen <jolesen at apple.com> writes:
> The TableGen language seems to be growing Lisp macros from two
> different directions.
>
> Che-Liang Chiou added a preprocessor with for loops, and David Greene
> added multidefs.
>
> It seems that some kind of macro facility is needed, perhaps we should
> discuss what it is supposed to look like?
Don't
2011 Oct 06
3
[LLVMdev] TableGen and Greenspun
The TableGen language seems to be growing Lisp macros from two different directions.
Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs.
It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like?
/jakob
2011 Oct 06
0
[LLVMdev] Enhacing TabelGen
...In this example:
[snip!]
> what if we instead did this:
>
> (Equivalent TableGen code with a for-loop)
> ----------------------------------------
> multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
> for nbit = [32, 32, 64, 64],
> op_suffix = [r, i, r, i],
> op_type = [RegF32, f32imm, RegF64, f64imm],
> op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
> def !strconcat(!strconcat("rr", !cast<string>(op_suffix)), "nbit")
> [...]
> }
> }
>
> Yes, it's...
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
...fpimm:$c))]>;
}
----------------------------------------
(Equivalent TableGen code with a for-loop)
----------------------------------------
multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
for nbit = [32, 32, 64, 64],
op_suffix = [r, i, r, i],
op_type = [RegF32, f32imm, RegF64, f64imm],
op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
def rr#op_suffix#nbit
: InstPTX<(outs RegF#nbit:$d),
(ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c),
!strconcat(opcstr, &quo...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
..."pasting" operation but I've found it
to be too limiting. In this example:
(Equivalent TableGen code with a for-loop)
----------------------------------------
multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
for nbit = [32, 32, 64, 64],
op_suffix = [r, i, r, i],
op_type = [RegF32, f32imm, RegF64, f64imm],
op_node_type = [RegF32, fpimm, RegF64, fpimm] in {
def rr#op_suffix#nbit
: InstPTX<(outs RegF#nbit:$d),
(ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c),
!strconcat(opcstr, &quo...