Displaying 12 results from an estimated 12 matches for "op_split".
2016 Sep 30
2
[PATCH v2] nv50/ir: constant fold OP_SPLIT
...738..d56b057 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -932,6 +932,22 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
Instruction *newi = i;
switch (i->op) {
+ case OP_SPLIT: {
+ uint8_t size = typeSizeof(i->dType);
+ DataType type = typeOfSize(size / 2, isFloatType(i->dType),
+ isSignedType(i->dType));
+ if (likely(type != TYPE_NONE)) {
+ uint64_t val = imm0.reg.data.u64;
+ uint16_t shift = size *...
2016 Sep 27
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...a85..fdddd71 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
Instruction *newi = i;
switch (i->op) {
+ case OP_SPLIT: {
+ uint16_t shift = 0;
+ DataType type = TYPE_NONE;
+ bld.setPosition(i, false);
+ if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
+ shift = 32;
+ type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE_S32;
+ }
+ if (i->sType == TYPE_U32 || i...
2016 Sep 28
0
[PATCH] nv50/ir: constant fold OP_SPLIT
...c/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> Instruction *newi = i;
>
> switch (i->op) {
> + case OP_SPLIT: {
> + uint16_t shift = 0;
> + DataType type = TYPE_NONE;
> + bld.setPosition(i, false);
> + if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
> + shift = 32;
> + type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE_S32;
> + }
>...
2016 Sep 30
0
[PATCH] nv50/ir: constant fold OP_SPLIT
...> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>>> @@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
>>> &imm0, int s)
>>> Instruction *newi = i;
>>>
>>> switch (i->op) {
>>> + case OP_SPLIT: {
>>> + uint16_t shift = 0;
>>> + DataType type = TYPE_NONE;
>>> + bld.setPosition(i, false);
>>> + if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
>>> + shift = 32;
>>> + type = (i->sType == TYP...
2016 Sep 30
0
[PATCH v2] nv50/ir: constant fold OP_SPLIT
...c/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -932,6 +932,22 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> Instruction *newi = i;
>
> switch (i->op) {
> + case OP_SPLIT: {
> + uint8_t size = typeSizeof(i->dType);
> + DataType type = typeOfSize(size / 2, isFloatType(i->dType),
> + isSignedType(i->dType));
Er wait, sorry, I might have confused matters here...
Why do you need to compute type at all? Why no...
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...codegen/nv50_ir_peephole.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> @@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
>> Instruction *newi = i;
>>
>> switch (i->op) {
>> + case OP_SPLIT: {
>> + uint16_t shift = 0;
>> + DataType type = TYPE_NONE;
>> + bld.setPosition(i, false);
>> + if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
>> + shift = 32;
>> + type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE...
2017 Aug 19
1
[PATCH] nv50/ra: Only increment DefValue counter if we are going to spill
...x e4f38c8e46..5034f8f989 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -1750,8 +1750,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
// multiple destinations that all need to be spilled (like OP_SPLIT).
unordered_set<Instruction *> to_del;
- for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
- ++d) {
+ for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();) {
Value *slot = mem ?
static_cast&...
2014 Sep 25
0
[PATCH] nv50/ir: avoid deleting pseudo instructions too early
...gt;asLValue();
Symbol *mem = it->second ? it->second->asSym() : NULL;
+ // Keep track of which instructions to delete later. Deleting them
+ // inside the loop is unsafe since a single instruction may have
+ // multiple destinations that all need to be spilled (like OP_SPLIT).
+ std::tr1::unordered_set<Instruction *> to_del;
+
for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
++d) {
Value *slot = mem ?
@@ -1579,7 +1585,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
d...
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before.
nothing really changed from the last version, just minor things.
Karol Herbst (5):
nv50/ir: restructure and rename postraconstantfolding pass
nv50/ir: implement mad post ra folding for nvc0+
gk110/ir: add LIMM form of mad
gm107/ir: add LIMM form of mad
nv50/ir: also do PostRaLoadPropagation for FMA
2014 May 30
4
[Bug 79462] New: [NVC0/Codegen] Shader compilation falis in spill logic
...with skyrimlauncher, when it's trying to
detect the graphics card.
dval is null, which means that something out there isn't an lvalue. Or, in this
case, apparently a null value??
(gdb) p *defi
$4 = {_vptr.Instruction = 0x86e570, next = 0x0, prev = 0x0, id = -1, serial =
27, op = nv50_ir::OP_SPLIT,
dType = nv50_ir::TYPE_B128, sType = nv50_ir::TYPE_B128, cc = nv50_ir::CC_TR,
rnd = nv50_ir::ROUND_N,
cache = nv50_ir::CACHE_CA, subOp = 0, encSize = 0, saturate = 0, join = 0,
fixed = 0, terminator = 0,
ftz = 0, dnz = 0, ipa = 0, lanes = 15, perPatch = 0, exit = 0, mask = 0,
postFactor =...
2014 Dec 02
0
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
...+d)
- lval->join->defs.remove(*d);
+ lval->join->defs.erase(*d);
lval->join = lval;
}
}
@@ -1553,8 +1553,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
// multiple destinations that all need to be spilled (like OP_SPLIT).
std::tr1::unordered_set<Instruction *> to_del;
- for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
- ++d) {
+ for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();) {
Value *slot = mem ?
st...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---