Displaying 4 results from an estimated 4 matches for "op_slct".
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op_set
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
...r_peephole.cpp
> @@ -973,6 +973,35 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> }
> break;
>
> + case OP_AND:
> + {
> + CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
> + if (!cmp || cmp->op == OP_SLCT)
how about if (cmp == NULL || ...) and kill the same condition later?
> + return;
> + if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
> + return;
> + if (imm0.reg.data.f32 != 1.0)
> + return;
> + if (cmp == NULL)
> +...
2014 May 10
1
[PATCH] nv50/ir: make sure to reverse cond codes on all the OP_SET variants
...sn)
return;
}
- if (insn->op == OP_SET)
+ if (insn->op == OP_SET || insn->op == OP_SET_AND ||
+ insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
insn->asCmp()->setCond = reverseCondCode(insn->asCmp()->setCond);
else
if (insn->op == OP_SLCT)
--
1.8.5.5
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
...eephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1023,27 +1023,53 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
case OP_AND:
{
- CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
- if (!cmp || cmp->op == OP_SLCT || cmp->getDef(0)->refCount() > 1)
- return;
- if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
- return;
- if (imm0.reg.data.f32 != 1.0)
- return;
- if (i->getSrc(t)->getInsn()->dType != TYPE_U32)
- return;
+ I...
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Pretty sure there's nothing wrong with it, but it looks odd in the code.
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++--
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)