Displaying 11 results from an estimated 11 matches for "op_neg".
2014 Jan 09
0
Handling UMAD with a negative modifier, or why glsl-fs-atan-3 was failing
So I figured out what was going on. The shader has a
UMAD TEMP[0].x, TEMP[0].xxxx, -TEMP[5].xxxx, TEMP[0].xxxx
instruction, in which the -TEMP[5].xxxx got emitted as
cvt neg u32 $r1 u32 $r1
If instead I fudge mkOp() to force a s32 dtype on OP_NEG, everything
starts to work. Similarly, if I fudge emitCVT to basically do the same
thing, it also works. (Of note -- changing both stype and dtype to s32
does _not_ work, which makes sense.) I'm not sure which approach is
the right one -- advice? It's a very short patch either way. Perhaps...
2015 Jan 05
0
[PATCH] nv50/ir: change the way float face is returned
...RP_FLAT, def, addr, NULL);
if (i->dType == TYPE_F32) {
- bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
- bld.mkOp2(OP_XOR, TYPE_U32, def, def, bld.mkImm(0xbf800000));
+ bld.mkOp2(OP_OR, TYPE_U32, def, def, bld.mkImm(0x00000001));
+ bld.mkOp1(OP_NEG, TYPE_S32, def, def);
+ bld.mkCvt(OP_CVT, TYPE_F32, def, TYPE_S32, def);
}
break;
case SV_NCTAID:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index ff48e94..04cd19e 100644
--- a/...
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++-------
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
2006 Dec 20
0
MATH function
I try to use function MATH or GoToIf for checking the negative value
but CLI shows an error as following.
exten => s,11,Set(bt=${MATH(-1>0)})
func_math.c:164 builtin_function_math: '' is not a valid number
exten => s,11,GoToIf($[-1 < 0]?20)
WARNING[12926]: ast_expr2.y:729 op_negate: non-numeric argument
It seems both functions can't accept negative number for comparison.
What function can I use to compare negative number?
2015 Jan 02
0
[PATCH] nv50/ir: Fold sat into mad
..., 0x1, 0x0 },
{ OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
- { OP_MAD, 0x7, 0x0, 0x0, 0x0, 0x6, 0x1, 0x1, 0x0 }, // special constraint
+ { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special constraint
{ OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
{ OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
{ OP_CVT, 0x1, 0x1, 0x0, 0x8, 0x0, 0x1, 0x1, 0x0 },
--
2.1.0
2014 Nov 23
3
[Bug 86618] New: [NV96] neg modifiers not working in MIN and MAX operations
...x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
+ { OP_MAX, 0x0, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
+ { OP_MIN, 0x0, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
{ OP_MAD, 0x7, 0x0, 0x0, 0x0, 0x6, 0x1, 0x1, 0x0 }, // special
constraint
{ OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
{ OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
After this change:
EMIT: presin f32 $r0 $r0 (8)
EMIT: sin f32 $r0 $r0 (8)
EMIT: mov u32 $r1 0x00000000 (8)
EMIT: neg f32 $r0 $r0 (8)
EMIT: max f32 $r2 $r0 $r1 (8)
--
You are receiving this mail because:
You are the assignee for the bug.
-------------...
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Pretty sure there's nothing wrong with it, but it looks odd in the code.
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++--
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
Retrieving the high 32 bits of a signed multiply is rather annoying. It
appears that the simplest way to do this is to compute the absolute
value of the arguments, and perform a u32 x u32 -> u64 operation. If the
arguments' signs differ, then negate the result. Since there is no u64
support in the cvt instruction, we have the perform the 2's complement
negation "by hand".
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
..., TYPE_F64, bld.getSSA(8), guess, guess)));
+
+ // Restore the sign on the output
+ bld.mkSplit(input, 4, i->getSrc(0));
+ bld.mkOp2(OP_AND, TYPE_U32, NULL, input[1], bld.loadImm(NULL, 0x80000000))
+ ->setFlagsDef(0, (pred = bld.getSSA(1, FILE_FLAGS)));
+ bld.mkOp1(OP_NEG, TYPE_F64, neg, guess)
+ ->setPredicate(CC_S, pred);
+ bld.mkMov(copy, guess)
+ ->setPredicate(CC_NS, pred);
+ guess = bld.mkOp2v(OP_UNION, TYPE_U64, bld.getSSA(8), neg, copy);
+ } else {
+ Value *half_input = bld.getSSA(8), *three_half = bld.getSSA(8);
+...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---