Displaying 20 results from an estimated 78 matches for "op_mov".
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...case TGSI_OPCODE_SHL:
>>> case TGSI_OPCODE_ISHR:
>>> case TGSI_OPCODE_USHR:
>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>> break;
>>> + case TGSI_OPCODE_POW:
>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> + mkOp1(OP_MOV, TYP...
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...> - case TGSI_OPCODE_POW:
> case TGSI_OPCODE_SHL:
> case TGSI_OPCODE_ISHR:
> case TGSI_OPCODE_USHR:
> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
> break;
> + case TGSI_OPCODE_POW:
> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
> + break...
2017 Apr 29
2
[PATCH] nv50/ir: we can't replace 0x0 with zero reg for SHLADD
...ndex 732e1a93b4..4815d6df07 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -740,7 +740,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb)
next = hi;
}
- if (i->op != OP_MOV && i->op != OP_PFETCH)
+ if (i->op != OP_MOV && i->op != OP_PFETCH && i->op != OP_SHLADD)
replaceZero(i);
}
}
--
2.12.2
2017 Apr 29
3
[PATCH] nv50/ir: optimmize shl(a, 0) to a
...m/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1284,6 +1284,11 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
case OP_SHL:
{
+ if (s == 1 && imm0.isInteger(0)) {
+ i->op = OP_MOV;
+ i->setSrc(1, NULL);
+ break;
+ }
if (s != 1 || i->src(0).mod != Modifier(0))
break;
// try to concatenate shifts
--
2.12.2
2015 Jan 09
3
[RESEND/PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...eau/codegen/nv50_ir_peephole.cpp
index 9a0bb60..6a3d515 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -997,6 +997,115 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->op = OP_MOV;
break;
}
+ case OP_CVT: {
+ Storage res;
+ bld.setPosition(i, true); /* make sure bld is init'ed */
+ switch(i->dType) {
+ case TYPE_U16:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate)
+ res.data.u16...
2014 Jun 03
8
[PATCH v2 0/4] Constant folding of new Instructions
And another try for constant folding of Instructions for nvc0.
Please Review this!
Thanks,
Tobias Klausmann
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant expressions
2015 Jan 10
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...veau/codegen/nv50_ir_peephole.cpp
index 9a0bb60..741c74f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -997,6 +997,87 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->op = OP_MOV;
break;
}
+ case OP_CVT: {
+ Storage res;
+ bld.setPosition(i, true); /* make sure bld is init'ed */
+ switch(i->dType) {
+ case TYPE_U16:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate)
+ res.data.u16...
2014 Jul 03
1
[PATCH v3 1/2] nv50/ir: Add support for the double Type to BuildUtil
...+{
+ union {
+ double f64;
+ uint64_t u64;
+ } u;
+ u.f64 = f;
+ return mkImm(u.u64);
+}
+
Value *
BuildUtil::loadImm(Value *dst, float f)
{
@@ -398,6 +409,12 @@ BuildUtil::loadImm(Value *dst, float f)
}
Value *
+BuildUtil::loadImm(Value *dst, double u)
+{
+ return mkOp1v(OP_MOV, TYPE_F64, dst ? dst : getScratch(8), mkImm(u));
+}
+
+Value *
BuildUtil::loadImm(Value *dst, uint32_t u)
{
return mkOp1v(OP_MOV, TYPE_U32, dst ? dst : getScratch(), mkImm(u));
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...L:
>>>> case TGSI_OPCODE_ISHR:
>>>> case TGSI_OPCODE_USHR:
>>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>>> break;
>>>> + case TGSI_OPCODE_POW:
>>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>> +...
2015 Jan 11
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...gt;>>>>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>>>>>> @@ -997,6 +997,87 @@ ConstantFolding::opnd(Instruction *i,
>>>>>> ImmediateValue
>>>>>> &imm0, int s)
>>>>>> i->op = OP_MOV;
>>>>>> break;
>>>>>> }
>>>>>> + case OP_CVT: {
>>>>>> + Storage res;
>>>>>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>>>>>> + switch(i...
2015 Jan 11
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...ex 9a0bb60..741c74f 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> @@ -997,6 +997,87 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
>> i->op = OP_MOV;
>> break;
>> }
>> + case OP_CVT: {
>> + Storage res;
>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>> + switch(i->dType) {
>> + case TYPE_U16:
>> + switch (i->sType) {
>> +...
2016 Sep 30
2
[PATCH v2] nv50/ir: constant fold OP_SPLIT
Split the source immediate value into two new values and create OP_MOV
instructions the two newly created values.
V2: get rid of special cases
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/src/gallium/d...
2015 Jan 11
2
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...hole.cpp
> index 21d20ca..aaf0d0d 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -997,6 +997,79 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> i->op = OP_MOV;
> break;
> }
> + case OP_CVT: {
> + Storage res;
> + bld.setPosition(i, true); /* make sure bld is init'ed */
> + switch(i->dType) {
> + case TYPE_U16:
> + switch (i->sType) {
> + case TYPE_F32:
> +...
2015 Jan 11
2
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...v50_ir_peephole.cpp
>>>>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>>>>> @@ -997,6 +997,79 @@ ConstantFolding::opnd(Instruction *i,
>>>>> ImmediateValue
>>>>> &imm0, int s)
>>>>> i->op = OP_MOV;
>>>>> break;
>>>>> }
>>>>> + case OP_CVT: {
>>>>> + Storage res;
>>>>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>>>>> + switch(i->dType) {
>>>...
2016 Sep 27
2
[PATCH] nv50/ir: constant fold OP_SPLIT
Split the source immediate value into two new values and create OP_MOV
instructions the two newly created values.
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir...
2014 Jul 05
1
[PATCH v4] nv50/ir: Handle OP_CVT when folding constant expressions
...eau/codegen/nv50_ir_peephole.cpp
index b89da43..c97f8f4 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -970,6 +970,127 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->op = OP_MOV;
break;
}
+ case OP_CVT: {
+ Storage res;
+ bld.setPosition(i, true); /* make sure bld is init'ed */
+ switch(i->dType) {
+ case TYPE_U16:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate) {
+ int32_t con...
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
On 28.09.2016 02:01, Ilia Mirkin wrote:
> On Tue, Sep 27, 2016 at 7:25 PM, Tobias Klausmann
> <tobias.johannes.klausmann at mni.thm.de> wrote:
>> Split the source immediate value into two new values and create OP_MOV
>> instructions the two newly created values.
>>
>> Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
>> ---
>> .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 23 ++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
&g...
2014 Jun 03
6
[PATCH v3 0/4] Constant folding of new Instructions
Yet another try for constant folding of Instructions for nvc0.
Please Review this again! (Hopefully the last time ;-) )
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
...nsn()->dType = TYPE_F32;
> + if (i->src(t).mod != Modifier(0)) {
> + assert(i->src(t).mod == Modifier(NV50_IR_MOD_NOT));
> + i->src(t).mod = Modifier(0);
> + cmp->setCond = reverseCondCode(cmp->setCond);
> + }
> + i->op = OP_MOV;
> + i->setSrc(s, NULL);
> + if (t) {
> + i->setSrc(0, i->getSrc(t));
> + i->setSrc(t, NULL);
> + }
> + }
> + break;
> +
> case OP_SHL:
> {
> if (s != 1 || i->src(0).mod != Modifier(0))
> diff...
2017 Apr 29
0
[PATCH] nv50/ir: we can't replace 0x0 with the zero reg for SHLADD
...ndex 732e1a93b4..4815d6df07 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -740,7 +740,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb)
next = hi;
}
- if (i->op != OP_MOV && i->op != OP_PFETCH)
+ if (i->op != OP_MOV && i->op != OP_PFETCH && i->op != OP_SHLADD)
replaceZero(i);
}
}
--
2.12.2