search for: op1

...39;m new in R and i need some help. Please, ¿do you know a function how can process cross tables for many variables and show the result in one table who look like this?: +----------------------------------------------------+ |------------------ | X variable | |----------------- | Xop1 | Xop2 | Xop3|.....| +----------------------------------------------------+ |Yvar1 | Total | %row..........................| | | Op1 | %row..........................| | | Op2 | %row..........................| |+---------------------------------------------------+ |Yvar2 | Op1 |...

I'm trying to implement *MUL_LOHI for my processor. My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit multiply. I tried this in ios2ISelDAGToDAG.cpp: /// Mul/Div with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1); AddToISelQueue(Op2); unsigned Op; Op = (Opcode == ISD::UMUL_LOHI ? Nios2::MULxu : Nios2::MULx); SDNode *Hi = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); SDNo...

...say I have 2 domains: - Virtual Mailbox Domain: example.local (internal domain) - Virtual Alias Domain: example.com (public domain) Every mail sent to @example.com is really sent to @example.local. I have a virtual alias that forward mails sent to support-abc at example.com is sent finally to: op1 at example.local Now, I'd want to every mail was sent to support-abc at example.com it triggers an autoreply vacation style. So, I've wrote and compiled a sieve filter, something like that and put in op1 at example.local sieve folder. But it fails complaining like that: nov 29 15:55:39 m...

Our architecture has 1-bit boolean predicate registers. I've defined comparison def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 = icmp eq i32 %3, 0 which compares the lowest...

...; > (snip) I've ran the good and bad bitcode files for a more compact example (attached) through llvm-bcanalyzer and diff: --- bad.xml 2013-01-09 22:57:58.691131492 +0400 +++ good.xml 2013-01-09 22:58:04.153133734 +0400 ... irrelevant ... <STRUCT_NAME abbrevid=7 op0=105 op1=46 op2=78 op3=105 op4=108 op5=67 op6=108 op7=97 op8=115 op9=115/> <STRUCT_NAMED abbrevid=8 op0=0 op1=0 op2=6/> <POINTER abbrevid=4 op0=7 op1=0/> - <STRUCT_ANON abbrevid=6 op0=0 op1=0 op2=6/> </TYPE_BLOCK_ID> <GLOBALVAR abbrevid=4 op0=8 op1=0 op2...

The langref says for the 'add' instruction: Syntax: <result> = add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nsw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw nsw add <ty> <op1>, <op2> ; yiel...

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > > > Code > > > %0 = zext i8 %data to i32 > %1 = zext i16 %crc to i32 > %2 = xor i32 %1, %0 > %3 = a...

...uctions i.e. 'no-overflow'. This is the updated solution devised in the discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-October/118257.html The proposed keywords: "nof" stands for 'no-overflow' Syntax: <result> = sdiv nof <ty> <op1>, <op2> ; yields ty:result <result> = udiv nof <ty> <op1>, <op2> ; yields ty:result Overview: If the keyword is present, the compiler can assume no zero values in the denominator. Moreover, for sdiv the division MIN_INT / -1 is prohibited. Otherwise, unde...

...Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>> >>> But then I end up having the following bug: >>> >>> Code >>> >>> %0 = zext i8 %data to i32 >>> %1 = zext i16 %crc to i32 >>> %2 =...

Hello. I've managed to create a bitcode file (attached; also available at [1]) which produces a series of identical errors when verified: | Global variable initializer type does not match global variable type! | %i.NilClass* @nil When ran through llvm-dis and recompiled, through, it verifies successfully. If I disassemble it one more time, the result is identical to the first

...;>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>> >>>> But then I end up having the following bug: >>>> >>>> Code >>>> >>>> %0 = zext i8 %data to i32 >>>> %1 = zext i1...

...tion, changing its type. That is, I would like to keep all characteristics of the old Instruction and create a new one only with a different type. I am trying create a new Instruction thus: %3 = add nsw i32 %1, %2 ; <i16> [#uses=2] //Old Instruction Value* Op0 = I->getOperand(0); Value* Op1 = I->getOperand(1); Value* V0 = new Value(Type::getInt16Ty(Op0->getContext()), Op0->getValueID()); Value* V1 = new Value(Type::getInt16Ty(Op1->getContext()), Op1->getValueID()); Instruction* newInst = BinaryOperator::CreateNSWAdd(V0, V1, "test"); errs() << "NewIn...

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >> >> But then I end up having the following bug: >> >> Code >> >> %0 = zext i8 %data to i32 >> %1 = zext i16 %crc to i32 >> %2 = xor i32 %1, %0 >> %3 =...

...---BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On Wed, 29 Nov 2017, Sergio Belkin wrote: Now, I'd want to every mail was sent to support-abc at example.com it triggers > an autoreply vacation style. > > So, I've wrote and compiled a sieve filter, something like that and put in > op1 at example.local sieve folder. > > But it fails complaining like that: > nov 29 15:55:39 muteriver.example.local dovecot[12549]: lmtp(12675, > op1 at example.local): CqNdF6sCH1qDMQAAcSFsIQ: sieve: msgid=< > ded22f3d-f1e3-157e-0667-ca73d851d1a8 at example.com>: discarding vacati...

...nput= data.frame(state1 = (1:500), state2 = (201:700) ) with data that partially overlap in terms of values. I want to minimize the assessment error of each state by using this function: err.th.scalar <- function(threshold, data){ state1 <- data$state1 state2 <- data$state2 op1l <- length(state1) op2l <- length(state2) op1.err <- sum(state1 <= threshold)/op1l op2.err <- sum(state2 >= threshold)/op2l total.err <- (op1.err + op2.err) return(total.err) } SO I'm trying to minimize the total error. This Total Error should be a U shap...

...$n, mem becomes btl $(n % 32), (mem + 4 * (n / 32)) + if (Name.startswith("bt") + && !(Name.endswith("b") || Name.endswith("w") || Name.endswith("l") || Name.endswith("q")) + && Operands.size() == 3) { + X86Operand &Op1 = *(X86Operand*)Operands.begin()[1]; + X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; + + if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) && + Op2.isMem() && isa<MCConstantExpr>(Op2.Mem.Disp)) { + int64_t Given_imm = cast<MCConstantEx...

...::iterator i = b.begin(), ie = b.end(); (i != ie) && (block_split == false);) { IntrinsicInst *ii = dyn_cast<IntrinsicInst>(&*i); ++i; if(ii) { switch (ii->getIntrinsicID()) { case Intrinsic::objectsize: { IRBuilder<> builder(ii->getParent(), ii); Value *op1 = ii->getArgOperand(0); //i8* uint64_t bit_size = op1->getType()->getPointerElementType()->getPrimitiveSizeInBits(); Value *result = ConstantInt::get(ii->getType(), bit_size); ii->replaceAllUsesWith(result); ii->removeFromParent(); delete ii; break; } } }...

Dear All, The InstCombine pass performs the following transformation. Z / (X / Y) => (Y * Z) / X This is performed only when operand Op1 ( (X/Y) in this case) has only one use in future. The code snippet is shown below. if (match(Op1, m_OneUse(m_FDiv(m_Value(X), m_Value(Y)))) && (!isa<Constant>(Y) || !isa<Constant>(Op0))) { // Z / (X / Y) => (Y * Z) / X Value *YZ = Builder.CreateFMulFM...

...a float and the new one is an int? float to signed int, float to unsigned int, or bitcast (only legal sometimes)? I am trying > create a new Instruction thus: > > %3 = add nsw i32 %1, %2 ; <i16> [#uses=2] //Old Instruction > > Value* Op0 = I->getOperand(0); > Value* Op1 = I->getOperand(1); > Value* V0 = new Value(Type::getInt16Ty(Op0->getContext()), > Op0->getValueID()); Hunh, Value's constructor is protected. In any event, Value is pure base. Constructing one this way will never get you what you want. If the ValueID indicates an Instruction,...

..., at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've defined comparison >>>>> >>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>>> >>>>> But then I end up having the following bug: >>>>> >>>>> Code >>>>> >>>>> %0 = zext i8 %data to i32 >&...