Displaying 3 results from an estimated 3 matches for "op0reg".
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obreg
2004 Jun 04
0
[LLVMdev] Some backend questions
...t; vregs: this is what the instruction
selector is about.
I recommend taking a look at the getReg(*) methods in the X86 instruction
selector. The basic code generation stage for an add, boiled down to its
simplest form, basically looks like this:
void visitAdd(BinaryOperator &B) {
unsigned Op0Reg = getReg(B.getOperand(0));
unsigned Op1Reg = getReg(B.getOperand(1));
unsigned DestReg = getReg(B);
unsigned Opcode = (get the opcode for the size of the add);
BuildMI(<where>, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
}
The nice thing about the "getReg" functiona...
2004 Jun 04
2
[LLVMdev] Some backend questions
Ok, I'm now trying to write instruction selector and have some questions
1. The MachineInstrBuilder has methods to add register operand and immediate
operand. However, what would be really nice is a method to add Value*. So, I
would write:
BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1));
and depending on whether the passed Value* is contant or instruction, the add
2004 Jun 07
2
[LLVMdev] Some backend questions
...> selector is about.
>
> I recommend taking a look at the getReg(*) methods in the X86 instruction
> selector. The basic code generation stage for an add, boiled down to its
> simplest form, basically looks like this:
>
> void visitAdd(BinaryOperator &B) {
> unsigned Op0Reg = getReg(B.getOperand(0));
> unsigned Op1Reg = getReg(B.getOperand(1));
> unsigned DestReg = getReg(B);
>
> unsigned Opcode = (get the opcode for the size of the add);
> BuildMI(<where>, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
> }
>
> The nice thing...