search for: on_selected_cpus

From: Julien Grall <julien.grall@citrix.com> Move smp_call_function and on_selected_cpus to common code. Signed-off-by: Julien Grall <julien.grall@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org> --- Changes in V2: - Add copyright header in xen/common/smp.c xen/arch/arm/gic.c | 3 ++ xen/arch/arm/sm...

...93379d662a36ff1731760eb0c AMD, powernow: Update P-state directly when _PSD''s CoordType is DOMAIN_COORD_TYPE_HW_ALL When _PSD''s CoordType is DOMAIN_COORD_TYPE_HW_ALL (i.e. shared_type is CPUFREQ_SHARED_TYPE_HW) which most often is the case on servers, there is no reason to go into on_selected_cpus() code, we call call transition_pstate() directly. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> diff -r 6d56e31fe1e1 -r 85190245a94d xen/arch/x86/acpi/cpufreq/powernow.c --- a/xen/arch/x86/acpi/cpufreq/powernow.c Wed Aug 15 09:41:21 2012 +0100 +++ b/xen/arch/x86/acpi/cpufreq/pow...

Currently cpufreq and xenpm are out of sync. Fix cpufreq reporting of if turbo mode is enabled or not. Fix xenpm to not decode for tristate, but a boolean. Signed-off-by: Jacob Shin <jacob.shin@amd.com> --- tools/misc/xenpm.c | 14 +++----------- xen/drivers/cpufreq/utility.c | 2 +- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/tools/misc/xenpm.c

...; + + if ( type != TEARDOWN_TYPE_EARLY ) + { + /* Ensure we are the boot CPU. */ + if ( GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid ) + { + printk("machine_teardown() not called on BSP\n"); + /* Send IPI to the boot CPU (logical cpu 0). */ + on_selected_cpus(cpumask_of_cpu(0), (void *)machine_teardown, + (void *)(unsigned long)type, 1, 0); + /* park us until smp_send_stop() sends us to shutdown handler */ + for ( ; ; ) + safe_halt(); + } + } watchdog_disable(); + console_start_sync(); - local_irq_enable(); - -...

...t;arch.vgic.lock); + if ( eoi ) { + /* this is not racy because we can''t receive another irq of the + * same type until we EOI it. */ + if ( cpu == smp_processor_id() ) + gic_irq_eoi((void*)virq); + else + on_selected_cpus(cpumask_of(cpu), gic_irq_eoi, (void*)virq, 0); + } + i++; } } diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index f9c1a6b..c5370d5 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -676,9 +676,14 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int ir...

...ch/x86/acpi/cpufreq/powernow.c index 2c9fea2..81ba17f 100644 --- a/xen/arch/x86/acpi/cpufreq/powernow.c +++ b/xen/arch/x86/acpi/cpufreq/powernow.c @@ -85,7 +85,7 @@ static int powernow_cpufreq_update (int cpuid, if (!cpumask_test_cpu(cpuid, &cpu_online_map)) return -EINVAL; - on_selected_cpus(cpumask_of(cpuid), update_cpb, policy, 1); + on_selected_cpus(policy->cpus, update_cpb, policy, 1); return 0; } -- 1.7.9.5

1: x86/mwait_idle: remove assumption of one C-state per MWAIT flag 2: x86/mwait_idle: export both C1 and C1E 3: x86/mwait_idle: initial C8, C9, C10 support Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com>

...t;arch.vgic.lock); + if ( eoi ) { + /* this is not racy because we can''t receive another irq of the + * same type until we EOI it. */ + if ( cpu == smp_processor_id() ) + gic_irq_eoi((void*)virq); + else + on_selected_cpus(cpumask_of(cpu), gic_irq_eoi, (void*)virq, 0); + } + i++; } } diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 8c96a0a..b2e486f 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -156,6 +156,7 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int...

...+ mov $1,%eax + mov %eax, nx_enabled-__PAGE_OFFSET no_execute_disable: pop %ebx #endif diff -r 13e258a58044 xen/arch/x86/smp.c --- a/xen/arch/x86/smp.c Wed Feb 14 11:13:40 2007 +0800 +++ b/xen/arch/x86/smp.c Wed Feb 14 14:59:49 2007 +0800 @@ -276,8 +276,9 @@ int on_selected_cpus( { struct call_data_struct data; unsigned int nr_cpus = cpus_weight(selected); - - ASSERT(local_irq_is_enabled()); + unsigned int self = cpu_isset(smp_processor_id(), selected); + + ASSERT(!self || local_irq_is_enabled()); if ( nr_cpus == 0 ) return 0; diff -r 13...

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

This patch series tidies up a few bits ofthe nested p2m code. The main thing it does is reorganize the locking so that most of the changes to nested p2m tables happen only under the p2m lock, and the nestedp2m lock is only needed to reassign p2m tables to new cr3 values. Changes since v1: - a few minor fixes - more sensible flushing policy in p2m_get_nestedp2m() - smoke-tested this time!

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See