search for: omap5432

...enabled once transmission started. This is because the semantic of THRE interrupt differs from common 8250 in TI''s implementation, which would be generated if TX FIFO below trigger level and cannot be cleared by simply write to THR once. Besides UART driver, arch timer initialization for OMAP5432 platform is also done in this patch series. v8 <- v7: - Only modifying THRE bit when enable/disable THRE interrupt in patch #4. v7 <- v6: - Fix a bug in patch #3. - Fix type problems Julien pointed out in patch #4. - Add vuart_info callback for omap-uart driver. v6 <- v5: - Add EARLY_UA...

Hi All, I am trying to run a RTOS as a guest on a OMAP5432 evm and am seeing a spurious interrupt problem when programming the virtual timer interrupts. My RTOS test case uses the A15 Virtual timer to create a timer instance. Once programmed, the virtual timer interrupt is injected into my guest's virtual CPU interface as expected and the interrupt is...