search for: olt

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2007 Nov 15
1
Why is model.matrix creating 2 columns for boolean?
I have a data frame "reading" that includes a logical variable "OLT" along with response variable "Reading" and predictor "True" (BOTH are numeric variables; it's "True" as in the true value). When I suppress the intercept, model.matrix gives me OLTTRUE and OLTFALSE columns. Why? Can I do anything to prevent it? > r &lt...
2015 Nov 02
2
[StructurizeCFG] Trouble with branches out of a loop
...x float> [ %5, %7 ], [ <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %0 ] %3 = extractelement <4 x float> %ret.02.i, i32 0 %4 = fadd fast float %3, 0xBFB99999A0000000 %5 = insertelement <4 x float> %ret.02.i, float %4, i32 0 %6 = fcmp olt float %4, 5.000000e-01 br i1 %6, label %_Z9get_colorDv2_f.exit, label %7 ; <label>:7 ; preds = %.lr.ph.i %8 = fadd fast float %i.03.i, 1.000000e+01 %9 = fcmp olt float %8, %1 br i1 %9, label %.lr.ph.i, label %._crit_edge.i ._crit_edge.i:...
2008 Nov 11
4
[LLVMdev] Invalid comparison instruction generation
...he backend I am targeting does not support all comparison instructions and trying to guess which instruction LLVM converted the current comparison instruction from and then converting to a supported instruction is not as simple as it can be. For example, I need to convert all ogt instructions to an olt instruction with LHS and RHS swapped, but since ogt is converted to ule, do I convert all ule into olt and swap? Thanks, Micah -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Monday, November 10, 2008 4:38 P...
2018 Nov 09
3
Proposed new min and max intrinsics
...should > return NaN if _either_ input is NaN, whereas the above will return NaN > if the second input (i.e. b) is NaN, but not if the first is. > > So we need to explicitly catch the case where a is NaN as well. For > minimum, that works out to something like: > > %3 = fcmp olt float %a, %b > %4 = select i1 %3, float %a, float %b ; (a < b) ? a : b > %5 = fcmp ord float %a, %a ; true if !isNaN(a) > %6 = select i1 %5, float %4, float %a ; if a was NaN, return a > > for the entire operation. The logic here is that if isNaN(a) || > isNaN(b), the...
2008 Nov 11
0
[LLVMdev] Invalid comparison instruction generation
...converting to a supported instruction is not > as simple as it can be. It's not a matter of guessing... you need to able to support all of the possible comparisons, since they can be introduced by optimizers at multiple levels. > For example, I need to convert all ogt instructions to an olt > instruction with LHS and RHS swapped, but since ogt is converted to ule, > do I convert all ule into olt and swap? The existing legalization infrastructure for condition codes is in SelectionDAGLegalize::LegalizeSetCCCondCode. If this isn't flexible enough, you might need to modify it...
2018 Nov 08
2
Proposed new min and max intrinsics
Alex, After looking into this a bit, it looks to me like the best thing to do for targets that do not natively support ISD::MINIMUM and ISD::MAXIMUM would be to fall back to a libcall, since implementing these operations in terms of existing operations is actually rather complicated. Do you think it would make sense to add builtin functions to compiler-rt to implement these operations, or is
2009 Jan 08
2
[LLVMdev] Loop elimination with floating point counter.
...| llvm-dis define void @func(...) nounwind { entry: br label %forinc forinc: ; preds = %forinc, %entry %i.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %add, %forinc ] ; <float> [#uses=1] %add = add float %i.0.reg2mem.0, 0x3FF3333340000000 ; <float> [#uses=2] %cmp = fcmp olt float %add, 1.000000e+03 ; <i1> [#uses=1] br i1 %cmp, label %forinc, label %afterfor afterfor: ; preds = %forinc ret void } What I expected is just one instruction "ret void" in function "func". Should I specify some specific optimizer pass for opt? If so, what is t...
2008 Jul 23
1
[LLVMdev] Extending vector operations
...operands being selected. The "simple" way to deal with this is to insert appropriate conversion code at uses of i1s, and pick a representation for a given i1 based on its SSA birthpoint. It's a little more ambiguous when you start adding phis into the mix, e.g.: a: %a1 = fcmp olt <2 x float> %f1, %f2 ; yields <2 x i1> br label %c b: %a2 = fcmp olt <2 x double> %d1, %d2 ; yields <2 x i1> br label %c c: %a3 = phi <2 x i1> [%a1, %a], [%a2, %b] select <2 x i1> %a3, %s1, %s2 ; where s1, s2 are <2 x i16> select <2 x i1> %a3,...
2008 Nov 11
0
[LLVMdev] Invalid comparison instruction generation
On Mon, Nov 10, 2008 at 3:06 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > With the above kernel run through llc with -march=x86 > -view-dag-combine1-dags I still see the ogt as the comparison operation, but > when I run it with llc -march=x86 -view-legalize-dags the ogt node has been > transformed into a ule. Okay... I can see that in the attached graph. > So, my
2008 Mar 31
5
[LLVMdev] Additional Optimization I'm Missing?
...on %OS_start1 = load double* %OS_start ; <double> [#uses=1] store double %OS_start1, double* %time br label %forcond forcond: ; preds = %forinc, %entry %time2 = load double* %time ; <double> [#uses=1] %OS_end3 = load double* %OS_end ; <double> [#uses=1] %forcond4 = fcmp olt double %time2, %OS_end3 ; <i1> [#uses=1] br i1 %forcond4, label %forbody, label %forafter forbody: ; preds = %forcond %birth_rate5 = load double* %birth_rate ; <double> [#uses=1] %population6 = load double* %population ; <double> [#uses=1] %multmp = mul double %birth_rate...
2010 Sep 29
0
[LLVMdev] spilling & xmm register usage
...%tmp34.i.i = fadd float %tmp33.i.i, 0xBFD6D1F0E0000000 > %tmp35.i.i = fmul float %tmp7.i.i, %tmp34.i.i > %tmp36.i.i = fadd float %tmp35.i.i, 0x3FD470BF40000000 > %tmp37.i.i = fmul float %tmp19.i.i, %tmp36.i.i > %tmp38.i.i = fsub float 1.000000e+00, %tmp37.i.i > %cmp.i.i = fcmp olt float %tmp53.i, 0.000000e+00 > br i1 %cmp.i.i, label %cond.then.i.i, label %phi.exit.i > > cond.then.i.i: ; preds = %entry.header.loop > %tmp43.i.i = fsub float 1.000000e+00, %tmp38.i.i > br label %phi.exit.i > > phi.exit.i:...
2019 Oct 08
2
PR43374 - when should comparing NaN values raise a floating point exception?
* Sanjay Patel <spatel at rotateright.com> [2019-10-08 08:07:10 -0400]: > On Tue, Oct 8, 2019 at 7:08 AM Szabolcs Nagy <nsz at port70.net> wrote: > > why is that ok? > > > > Because there are no FP exceptions/signals for this IR opcode: > http://llvm.org/docs/LangRef.html#floating-point-environment so llvm cannot support an iso c frontend on an ieee754 target?
2009 Jan 08
0
[LLVMdev] Loop elimination with floating point counter.
...{ > entry: > br label %forinc > > forinc: ; preds = %forinc, %entry > %i.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %add, %forinc > ] ; <float> [#uses=1] > %add = add float %i.0.reg2mem.0, 0x3FF3333340000000 ; <float> > [#uses=2] > %cmp = fcmp olt float %add, 1.000000e+03 ; <i1> [#uses=1] > br i1 %cmp, label %forinc, label %afterfor > > afterfor: ; preds = %forinc > ret void > } > > What I expected is just one instruction "ret void" in function "func". > > Should I specify some specifi...
2010 Sep 29
3
[LLVMdev] spilling & xmm register usage
Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under
2008 Nov 10
2
[LLVMdev] Invalid comparison instruction generation
I have a simple program that generates correct intermediate representation. However, when working on my backend, and my lowering function gets called. The comparison operation is flipped via an invalid transformation. i.e. gt ==> le, lt ==> ge etc.. define void @test_fc_if_gt(double %x, double %y, double addrspace(11)* %result) { entry: %x.addr = alloca double ;
2009 Jan 08
2
[LLVMdev] Loop elimination with floating point counter.
...; preds = %forinc, %entry >> %i.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %add, %forinc >> ] ; <float> [#uses=1] >> %add = add float %i.0.reg2mem.0, 0x3FF3333340000000 ; <float> >> [#uses=2] >> %cmp = fcmp olt float %add, 1.000000e+03 ; <i1> [#uses=1] >> br i1 %cmp, label %forinc, label %afterfor >> >> afterfor: ; preds = %forinc >> ret void >> } >> >> What I expected is just one instruction "ret void" in fun...
2017 Mar 15
2
Speculative execution of FP divide Instructions - Call-Graph Simplify
..., [ 1.000000e+00, %entry ] ret double %a_factor } ``` Here, the conditional is guarding a possible division by zero. However if I run CGSimplify on this I get: ``` define double @foo(double %a1, double %a2, double %a3) local_unnamed_addr #0 { entry: %a_mul = fmul double %a1, %a2 %a_cmp = fcmp olt double %a_mul, %a3 %a_div = fdiv double %a_mul, %a3 %a_factor = select i1 %a_cmp, double %a_div, double 1.000000e+00 ret double %a_factor } ``` This will cause a FP arithmetic exception, and the application will get a SIGFPE signal. The code that drives the change in the optimizer relies on `...
2017 Mar 15
3
Speculative execution of FP divide Instructions - Call-Graph Simplify
...conditional is guarding a possible division by zero. >> However if I run CGSimplify on this I get: >> ``` >> define double @foo(double %a1, double %a2, double %a3) >> local_unnamed_addr #0 { >> entry: >> %a_mul = fmul double %a1, %a2 >> %a_cmp = fcmp olt double %a_mul, %a3 >> %a_div = fdiv double %a_mul, %a3 >> %a_factor = select i1 %a_cmp, double %a_div, double 1.000000e+00 >> ret double %a_factor >> } >> ``` >> This will cause a FP arithmetic exception, and the application will >> get a SIGFPE sign...
2016 Mar 16
3
RFC: A change in InstCombine canonical form
...-- entry: %0 = load float, float* %input, align 4, !tbaa !1 for.cond: ; preds = %for.body, %entry %max_value.0 = phi float [ %0, %entry ], [ %.sroa.speculated, %for.body ] for.body: %1 = load float, float* %arrayidx1, align 4, !tbaa !1 %cmp.i = fcmp olt float %max_value.0, %1 %.sroa.speculate.load.true = load float, float* %arrayidx1, align 4, !tbaa !1 %.sroa.speculated = select i1 %cmp.i, float %.sroa.speculate.load.true, float %max_value.0 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.o...
2007 Mar 25
2
[LLVMdev] Live intervals and aliasing registers problem
...takes is two registers which alias a third to have overlapping live ranges, such as when the following code is compiled. define void @_Z3foov() { entry: %tmp1 = tail call float @_Z3onev( ) ; <float> [#uses=2] %tmp2 = tail call float @_Z3twov( ) ; <float> [#uses=2] %tmp5 = fcmp olt float %tmp1, %tmp2 ; <i1> [#uses=1] %retval = select i1 %tmp5, float %tmp1, float %tmp2 ; <float> [#uses=0] ret void } Does the fact that V4R0 is considered live-in mean I need to fix my target code, or does the live interval analysis need fixing to handle this corner case? A...