search for: offsetedinfo

Displaying 4 results from an estimated 4 matches for "offsetedinfo".

2015 Jun 16
2
[LLVMdev] Replacing a Reg MachineOperand with a non-Reg MachineOperand?
...ould solve your >> problem. >> >> 2015-06-16 9:15 GMT-07:00 Ryan Taylor <ryta1203 at gmail.com>: >> >>> So I have this for ChangeToGlobalAddress(const GlobalValue *GV): >>> >>> ... >>> OpKind = MO_GlobalAddress; >>> Contents.OffsetedInfo.Val.GV = GV; >>> >>> and then I use the function like this: >>> >>> >>> MI->getOperand(1).ChangeToGlobalAddress(MII->getOperand(1).getOperand.getGlobal()); >>> >>> The operand ends up being replaced with the global; however, it...
2012 Mar 30
1
[LLVMdev] load instruction memory operands value null
Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;
2015 Jun 16
2
[LLVMdev] Replacing a Reg MachineOperand with a non-Reg MachineOperand?
...perand. Just add 'setOffset(0)' to your change method and that should solve your problem. 2015-06-16 9:15 GMT-07:00 Ryan Taylor <ryta1203 at gmail.com>: > So I have this for ChangeToGlobalAddress(const GlobalValue *GV): > > ... > OpKind = MO_GlobalAddress; > Contents.OffsetedInfo.Val.GV = GV; > > and then I use the function like this: > > > MI->getOperand(1).ChangeToGlobalAddress(MII->getOperand(1).getOperand.getGlobal()); > > The operand ends up being replaced with the global; however, it's also > adding a large constant immediate value wi...
2015 Jun 16
2
[LLVMdev] Replacing a Reg MachineOperand with a non-Reg MachineOperand?
Tom, My current example is a global address; however, it could be any operand in theory. The arch allows for direct mem op support for ex instructions, so it could be any type of address or any type of imm or any type of register. For example, we are using intrinsics for some instructions since LLVM does not support them. Table gen does not allow for matching to direct mem op because the