Displaying 5 results from an estimated 5 matches for "offsetb".
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2016 Feb 03
2
[buildSchedGraph] memory dependencies
...;
+ const Value *VALb = MMOb->getValue();
+ if (VALa == VALb &&
+ !MIa->hasUnmodeledSideEffects() && !MIb->hasUnmodeledSideEffects() &&
+ !MIa->hasOrderedMemoryRef() && !MIb->hasOrderedMemoryRef()) {
+ int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
+ int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
+ int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
+ int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
+ int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
+ if (LowOffset...
2017 Jul 27
2
Are there some strong naming conventions in TableGen?
...n=4)> t0, Constant:i16<3>, FrameIndex:i16<1>, undef:i16
I have defined the following instruction and associated DAG pattern.
def MOVSUTO_A_i32o : CLPFPU_A_i32o_Inst<0b1000001101,
(ins IMM16Operand:$ImmA,FPUaOffsetOperand:$OffsetB),
(outs ),
[],
"movsuto_a\t$ImmA,$OffsetB","I32O",
[(store (i16 IMM16Operand:$ImmA), FP...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...nstruction on high and low parts of 32 bits registers.
So, I have to generate a sequence of two native instructions (LOR followed by HOR).
I've introduced an Pseudo instruction with a custom inserter.
def OR_A_oo : CLPPseudoInst<(ins FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),(outs FPUaROUTADDRegisterClass:$FA_ROUTADD),
[], [RFLAGA],
"# OR_A_oo",
[(set FPUaROUTADDRegiste...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...TMUL.
I have defined FPUaROUTMULRegisterClass containing only FA_ROUTMUL.
During the instruction lowering, in order to avoid frequent spill out of FA_ROUTMUL, I systematically copy the result of FMUL_A_oo to a virtual register through a COPY_TO_REGCLASS.
def : Pat<(fdiv f32:$OffsetA, f32:$OffsetB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),FPUaOffsetClass)>;
The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.
These COPY are at positions 64B and 11...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
Hi,
I've instruction scheduling problem that I cannot further investigate by myself... Could someone give me some clues?
After Instruction selection, here is part of the generated instruction.
NOP
MOV_AB_ro @s1, %fab_roff0
%6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5
MOVSUTO_A_iSLo 24575, def %7;