Displaying 3 results from an estimated 3 matches for "offseta".
Did you mean:
offset
2016 Feb 03
2
[buildSchedGraph] memory dependencies
...alue *VALa = MMOa->getValue();
+ const Value *VALb = MMOb->getValue();
+ if (VALa == VALb &&
+ !MIa->hasUnmodeledSideEffects() && !MIb->hasUnmodeledSideEffects() &&
+ !MIa->hasOrderedMemoryRef() && !MIb->hasOrderedMemoryRef()) {
+ int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
+ int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
+ int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
+ int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
+ int LowWidth = (LowOffset == OffsetA) ? Widt...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...arget only provide native instruction on high and low parts of 32 bits registers.
So, I have to generate a sequence of two native instructions (LOR followed by HOR).
I've introduced an Pseudo instruction with a custom inserter.
def OR_A_oo : CLPPseudoInst<(ins FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),(outs FPUaROUTADDRegisterClass:$FA_ROUTADD),
[], [RFLAGA],
"# OR_A_oo",...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...egister FA_ROUTMUL.
I have defined FPUaROUTMULRegisterClass containing only FA_ROUTMUL.
During the instruction lowering, in order to avoid frequent spill out of FA_ROUTMUL, I systematically copy the result of FMUL_A_oo to a virtual register through a COPY_TO_REGCLASS.
def : Pat<(fdiv f32:$OffsetA, f32:$OffsetB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),FPUaOffsetClass)>;
The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.
These COPY are at positi...