search for: offset_high

...desc(gate_desc *gate, const struct idt_data *d) +{ + unsigned long addr = (unsigned long) d->addr; + + gate->offset_low = (u16) addr; + gate->segment = (u16) d->segment; + gate->bits = d->bits; + gate->offset_middle = (u16) (addr >> 16); +#ifdef CONFIG_X86_64 + gate->offset_high = (u32) (addr >> 32); + gate->reserved = 0; +#endif +} + extern unsigned long system_vectors[]; extern void load_current_idt(void); diff --git a/arch/x86/include/asm/desc_defs.h b/arch/x86/include/asm/desc_defs.h index 5621fb3f2d1a..f7e7099af595 100644 --- a/arch/x86/include/asm/desc_...

Based on the original patch by Christoph Bumiller, but since it depends on kernel support patched I cannot push it yet. The changes are that I enable vblank by default, and offset takes OFFSET_HIGH/LOW instead of something relative to notifier_bo. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- diff --git a/man/nouveau.man b/man/nouveau.man index 7c72907..8765569 100644 --- a/man/nouveau.man +++ b/man/nouveau.man @@ -79,7 +79,7 @@ Enable or disable wfb, only...

...PTR_MIDDLE(x) (((unsigned long)(x) >> 16) & 0xFFFF) #define PTR_HIGH(x) ((unsigned long)(x) >> 32) +#define DESC_ADDRESS(d) ((unsigned long)((unsigned long)d.base2 << 32) \ + | (d.base1 << 16) | d.base0) + +#define GATE_ADDRESS(g) ((unsigned long)((unsigned long)g.offset_high << 32) \ + | (g.offset_middle << 16) | g.offset_low) enum { DESC_TSS = 0x9, DESC_LDT = 0x2, --

...PTR_MIDDLE(x) (((unsigned long)(x) >> 16) & 0xFFFF) #define PTR_HIGH(x) ((unsigned long)(x) >> 32) +#define DESC_ADDRESS(d) ((unsigned long)((unsigned long)d.base2 << 32) \ + | (d.base1 << 16) | d.base0) + +#define GATE_ADDRESS(g) ((unsigned long)((unsigned long)g.offset_high << 32) \ + | (g.offset_middle << 16) | g.offset_low) enum { DESC_TSS = 0x9, DESC_LDT = 0x2, --

...L_CS; > + entry.bits.type = GATE_TRAP; ^^^ I realize we're not running a real kernel here, but GATE_TRAP is madness. Please use GATE_INTERRUPT. > + entry.bits.p = 1; > + entry.offset_middle = (u16)((address >> 16) & 0xffff); > + entry.offset_high = (u32)(address >> 32); > + > + memcpy(&boot_idt[vector], &entry, sizeof(entry)); > +} > + > +/* Have this here so we don't need to include <asm/desc.h> */ > +static void load_boot_idt(const struct desc_ptr *dtr) > +{ > + asm volatile(&q...

...)handler; + gate_desc entry; + + memset(&entry, 0, sizeof(entry)); + + entry.offset_low = (u16)(address & 0xffff); + entry.segment = __KERNEL_CS; + entry.bits.type = GATE_TRAP; + entry.bits.p = 1; + entry.offset_middle = (u16)((address >> 16) & 0xffff); + entry.offset_high = (u32)(address >> 32); + + memcpy(&boot_idt[vector], &entry, sizeof(entry)); +} + +/* Have this here so we don't need to include <asm/desc.h> */ +static void load_boot_idt(const struct desc_ptr *dtr) +{ + asm volatile("lidt %0"::"m" (*dtr)); +} + +/* S...

...)handler; + gate_desc entry; + + memset(&entry, 0, sizeof(entry)); + + entry.offset_low = (u16)(address & 0xffff); + entry.segment = __KERNEL_CS; + entry.bits.type = GATE_TRAP; + entry.bits.p = 1; + entry.offset_middle = (u16)((address >> 16) & 0xffff); + entry.offset_high = (u32)(address >> 32); + + memcpy(&boot_idt[vector], &entry, sizeof(entry)); +} + +/* Have this here so we don't need to include <asm/desc.h> */ +static void load_boot_idt(const struct desc_ptr *dtr) +{ + asm volatile("lidt %0"::"m" (*dtr)); +} + +/* S...

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

...he hypervisor from needing any data sections, + * we need to hard code the difference between what the hypervisor + * may put into the GS base, and what we let the guest put in. + * We allow the guest to put in "Kernel addresses" to simplify + * the guest PDA code. + */ +#define LGUEST_HV_OFFSET_HIGH 0xffffffff +#define LGUEST_HV_OFFSET_LOW 0xff000000 + +#define LGUEST_NMI_IST 7 + +#define LGUEST_MAGIC 0x6c6775657374 /* "lguest" */ + +#ifndef __ASSEMBLY__ +#include <asm/lguest.h> + +extern void switch_to_guest(struct lguest_vcpu *); +extern unsigned long hcall_teste; +extern un...

...he hypervisor from needing any data sections, + * we need to hard code the difference between what the hypervisor + * may put into the GS base, and what we let the guest put in. + * We allow the guest to put in "Kernel addresses" to simplify + * the guest PDA code. + */ +#define LGUEST_HV_OFFSET_HIGH 0xffffffff +#define LGUEST_HV_OFFSET_LOW 0xff000000 + +#define LGUEST_NMI_IST 7 + +#define LGUEST_MAGIC 0x6c6775657374 /* "lguest" */ + +#ifndef __ASSEMBLY__ +#include <asm/lguest.h> + +extern void switch_to_guest(struct lguest_vcpu *); +extern unsigned long hcall_teste; +extern un...

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by

From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or

From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build