search for: of_pci_map_rid

...the ranges in a portable way? This would minimize the dependency on dt bindings and ACPI, enabling support for systems that have neither but do have virtio e.g. through pci. > Should we > indicate something in dmesg (and/or sysfs) about devices that bypass > it? > > > Relaxing of_pci_map_rid also allows the msi-map property to have gaps, > > s/of_pci_map_rid/of_pci_map_rid()/ > > > which is invalid since MSIs always reach an MSI controller. Thankfully > > Linux will error out later, when attempting to find an MSI domain for the > > device. > > Not cl...

...ult upon any transaction due to no valid stream table entry being programmed (not even a bypass one). I reckon it's a sufficiently unusual case that keeping some sort of message probably is worthwhile (at pr_info rather than pr_err) in case someone does hit it by mistake. >> Relaxing of_pci_map_rid also allows the msi-map property to have gaps, At worst, I suppose we could always add yet another parameter for each caller to choose whether a missing entry is considered an error or not. Robin. > s/of_pci_map_rid/of_pci_map_rid()/ > >> which is invalid since MSIs always reach an...

Implement the virtio-iommu driver, following specification v0.8 [1]. Changes since v2 [2]: * Patches 2-4 allow virtio-iommu to use the PCI transport, since QEMU would like to phase out the MMIO transport. This produces a complex topology where the programming interface of the IOMMU could appear lower than the endpoints that it translates. It's not unheard of (e.g. AMD IOMMU), and the

Implement the virtio-iommu driver, following specification v0.8 [1]. Changes since v2 [2]: * Patches 2-4 allow virtio-iommu to use the PCI transport, since QEMU would like to phase out the MMIO transport. This produces a complex topology where the programming interface of the IOMMU could appear lower than the endpoints that it translates. It's not unheard of (e.g. AMD IOMMU), and the