Displaying 4 results from an estimated 4 matches for "odeh".
Did you mean:
ode
2016 Dec 08
0
[RFC] Enable "#pragma omp declare simd" in the LoopVectorizer
On 8 December 2016 at 18:11, Tian, Xinmin via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> For name mangling, we have to follow certain rules of C/C++ (e.g. prefix needs to _ZVG ....). David Majnemer who is the owner and stakeholder for approval for Clang and LLVM. Also, we need to pay attention to GCC compatibility. I would suggest you look into how GCC VectorABI can be extended
2016 Dec 12
0
[RFC] Enable "#pragma omp declare simd" in the LoopVectorizer
...Majnemer who is the owner and stakeholder for
>approval for Clang and LLVM. Also, we need to pay attention to GCC
>compatibility. I would suggest you look into how GCC VectorABI can be
>extended support your Arch.
>
>Thanks,
>Xinmin
>
>-----Original Message-----
>From: Odeh, Saher
>Sent: Thursday, December 8, 2016 3:49 AM
>To: Tian, Xinmin <xinmin.tian at intel.com>; llvm-dev at lists.llvm.org;
>Francesco.Petrogalli at arm.com
>Cc: nd <nd at arm.com>; Masten, Matt <matt.masten at intel.com>; Hal Finkel
><hfinkel at anl.gov>; Zak...
2016 Dec 08
6
[RFC] Enable "#pragma omp declare simd" in the LoopVectorizer
...prefix needs to _ZVG ....). David Majnemer who is the owner and stakeholder for approval for Clang and LLVM. Also, we need to pay attention to GCC compatibility. I would suggest you look into how GCC VectorABI can be extended support your Arch.
Thanks,
Xinmin
-----Original Message-----
From: Odeh, Saher
Sent: Thursday, December 8, 2016 3:49 AM
To: Tian, Xinmin <xinmin.tian at intel.com>; llvm-dev at lists.llvm.org; Francesco.Petrogalli at arm.com
Cc: nd <nd at arm.com>; Masten, Matt <matt.masten at intel.com>; Hal Finkel <hfinkel at anl.gov>; Zaks, Ayal <ayal.zak...
2016 Nov 30
5
[RFC] Enable "#pragma omp declare simd" in the LoopVectorizer
Dear all,
I have just created a couple of differential reviews to enable the
vectorisation of loops that have function calls to routines marked with
“#pragma omp declare simd”.
They can be (re)viewed here:
* https://reviews.llvm.org/D27249
* https://reviews.llvm.org/D27250
The current implementation allows the loop vectorizer to generate vector
code for source file as:
#pragma omp declare