Displaying 6 results from an estimated 6 matches for "nxv2i64".
2017 Mar 07
2
[RFC][SVE] Extend vector types to support SVE registers.
...Elements> <ElementType>
it seems logical to use the same scheme for SVE but also incorporate the implicit (VL x) to distinguish from existing vector types. Hence we are proposing each vector MVT have a scalable vector MVT equivalent.
MVT::v2i32 -> MVT::nxv2i32
MVT::v2i64 -> MVT::nxv2i64
MVT::v4i32 -> MVT::nxv4i32
MVT::v4i64 -> MVT::nxv4i64
....likewise for all <#Elements> and <ElementType> combinations
The resulting SVE instruction selection is...
(1) Pat<(nxv2i64 (add (nxv2i64 $zn), (nxv2i64 $zm))), ADD_D_ZZZ // New SVE pattern
(2) Pat<(nxv4i32 (add...
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...4 x double> into two
> separate <scalable 2 x double> values.
>
> ``
> %vscale64 = call i64 @llvm.experimental.vector.vscale.64()
> ;; Stepvector generates the element ids for first subvector
> %sv1 = call <scalable 2 x i64> @llvm.experimental.vector.stepvector.nxv2i64()
> ;; Add vscale * 2 to get the starting element for the second subvector
> %ec = mul i64 %vscale64, 2
> %ec.ins = insertelement <scalable 2 x i64> undef, i64 %ec, i32 0
> %ec.splat = shufflevector <scalable 2 x i64> %9, <scalable 2 x i64> undef, <scalable 2 x...
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...x double> values.
> >
> > ``
> > %vscale64 = call i64 @llvm.experimental.vector.vscale.64()
> > ;; Stepvector generates the element ids for first subvector
> > %sv1 = call <scalable 2 x i64>
> @llvm.experimental.vector.stepvector.nxv2i64()
> > ;; Add vscale * 2 to get the starting element for the second
> subvector
> > %ec = mul i64 %vscale64, 2
> > %ec.ins = insertelement <scalable 2 x i64> undef, i64 %ec, i32 0
> > %ec.splat = shufflevector <scalable 2 x i64> %9, <...
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...double> into two
> separate <scalable 2 x double> values.
>
> ``
> %vscale64 = call i64 @llvm.experimental.vector.vscale.64()
> ;; Stepvector generates the element ids for first subvector
> %sv1 = call <scalable 2 x i64> @llvm.experimental.vector.stepvector.nxv2i64()
> ;; Add vscale * 2 to get the starting element for the second subvector
> %ec = mul i64 %vscale64, 2
> %ec.ins = insertelement <scalable 2 x i64> undef, i64 %ec, i32 0
> %ec.splat = shufflevector <scalable 2 x i64> %9, <scalable 2 x i64> undef, <scala...
2016 Nov 04
2
[RFC] Supporting ARM's SVE in LLVM
...d this
parameter's meaning to become implicitly multiplied by `n` to match its main
usage.
The change has no effect when applied to non-scalable vectors, because `n ==
1`. No target specific code is affected and in many cases common code becomes
compatible with scalable vectors. For example:
`nxv2i64 extract_subvector(nxv4i64, 2)`
The real first lane becomes `n * 2`, resulting in the extraction of the top
half of the input vector. This maintains the intension of the original code for
both scalable and non-scalable vectors.
For common code that truly requires an absolute index we recommend a n...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi,
Now that Sander has committed enough MC support for SVE, here's an updated
RFC for variable length vector support with a set of 14 patches (listed at the end)
to demonstrate code generation for SVE using the extensions proposed in the RFC.
I have some ideas about how to support RISC-V's upcoming extension alongside
SVE; I'll send an email with some additional comments on