search for: nxv1i32

...w do I use half- and quarter-width vectors? Must I resort to predication? To split a <scalable 2 x double> in half, you'd use a shufflevector in much the same way you would for fixed-length vector types. e.g. `` %sv = call <scalable 1 x i32> @llvm.experimental.vector.stepvector.nxv1i32() %halfvec = shufflevector <scalable 2 x double> %fullvec, <scalable 2 x double> undef, <scalable 1 x i32> %sv `` You can't split it any further than a <scalable 1 x <ty>>, since there may only be one element in the actual hardware vector at runtime. The same re...

Hi all, On Tue, 7 Apr 2020 at 11:04, Renato Golin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Tue, 7 Apr 2020 at 09:30, Kai Wang via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > LMUL = 1 LMUL = 2 LMUL = 4 LMUL = 8 > > int64_t | vscale x 1 x i64 | vscale x 2 x i64 | vscale x 4 x i64 | vscale x 8 x i64

Hi, Now that Sander has committed enough MC support for SVE, here's an updated RFC for variable length vector support with a set of 14 patches (listed at the end) to demonstrate code generation for SVE using the extensions proposed in the RFC. I have some ideas about how to support RISC-V's upcoming extension alongside SVE; I'll send an email with some additional comments on