search for: nvsync

nv50_head_atomic_duplicate_state() makes a copy of nv50_head_atom struct. This patch adds copying of struct member named "or", which previously was left uninitialized in the duplicated structure. Due to this bug, incorrect nhsync and nvsync values were sometimes used. In my particular case, that lead to a mismatch between the output resolution of the graphics device (GeForce GT 630 OEM) and the reported input signal resolution on the display. xrandr reported 1680x1050, but the display reported 1280x1024. As a result of this mismatch,...

...tty much narrowed it down to that. I'm wondering if anyone has ever had such problems or knows of some special sync that is needed for m2mf. I'm doing copy, map, unmap, copy back for pretty much everything. About 10 secs of gtkperf is enough to trigger it. I've gone as far as placing an NVSync after every dma transfer. I'd appreciate any kind of hint. Maarten.

...d, 1 insertions(+), 1 deletions(-) diff --git a/src/nouveau_exa.c b/src/nouveau_exa.c index b656ca7..20ad380 100644 --- a/src/nouveau_exa.c +++ b/src/nouveau_exa.c @@ -259,7 +259,7 @@ nouveau_exa_mark_sync(ScreenPtr pScreen) static void nouveau_exa_wait_marker(ScreenPtr pScreen, int marker) { - NVSync(xf86Screens[pScreen->myNum]); + return; } static Bool -- 1.6.1.3

...> > > nv50_head_atomic_duplicate_state() makes a copy of nv50_head_atom > > struct. This patch adds copying of struct member named "or", which > > previously was left uninitialized in the duplicated structure. > > > > Due to this bug, incorrect nhsync and nvsync values were sometimes used. > > In my particular case, that lead to a mismatch between the output > > resolution of the graphics device (GeForce GT 630 OEM) and the reported > > input signal resolution on the display. xrandr reported 1680x1050, but > > the display reported 1...

...s at gmail.com> wrote: > > nv50_head_atomic_duplicate_state() makes a copy of nv50_head_atom > struct. This patch adds copying of struct member named "or", which > previously was left uninitialized in the duplicated structure. > > Due to this bug, incorrect nhsync and nvsync values were sometimes used. > In my particular case, that lead to a mismatch between the output > resolution of the graphics device (GeForce GT 630 OEM) and the reported > input signal resolution on the display. xrandr reported 1680x1050, but > the display reported 1280x1024. As a resul...

...eam commit c4a52d669690423ee3c99d8eda1e69cd0821fcad ] nv50_head_atomic_duplicate_state() makes a copy of nv50_head_atom struct. This patch adds copying of struct member named "or", which previously was left uninitialized in the duplicated structure. Due to this bug, incorrect nhsync and nvsync values were sometimes used. In my particular case, that lead to a mismatch between the output resolution of the graphics device (GeForce GT 630 OEM) and the reported input signal resolution on the display. xrandr reported 1680x1050, but the display reported 1280x1024. As a result of this mismatch,...

First the background: Debian bug #513904 with the NV driver: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=513904 The NV driver started hanging inexplicably in nvSync(). I suspected, and still suspect, hardware problems with this card - an NVidia Quadro 3500 (it came with the machine, I didn't choose it). It was behaving well until late January. The card however passed the diagnostic tests on the HP Insight Diagnostics CD even after the problem started to o...

..._head_atomic_duplicate_state() makes a copy of nv50_head_atom > > > struct. This patch adds copying of struct member named "or", which > > > previously was left uninitialized in the duplicated structure. > > > > > > Due to this bug, incorrect nhsync and nvsync values were sometimes used. > > > In my particular case, that lead to a mismatch between the output > > > resolution of the graphics device (GeForce GT 630 OEM) and the reported > > > input signal resolution on the display. xrandr reported 1680x1050, but > > > th...

...ne __NV50_KMS_ATOM_H__ #define nv50_atom(p) container_of((p), struct nv50_atom, state) #include <drm/drm_atomic.h> +#include "crc.h" + +struct nouveau_encoder; struct nv50_atom { struct drm_atomic_state state; @@ -115,9 +118,12 @@ struct nv50_head_atom { u8 nhsync:1; u8 nvsync:1; u8 depth:4; + u8 crc_raster:2; u8 bpc; } or; + struct nv50_crc_atom crc; + /* Currently only used for MST */ struct { int pbn; @@ -135,6 +141,7 @@ struct nv50_head_atom { bool ovly:1; bool dither:1; bool procamp:1; + bool crc:1; bool or:1; }; u16 mask; @...

...ne __NV50_KMS_ATOM_H__ #define nv50_atom(p) container_of((p), struct nv50_atom, state) #include <drm/drm_atomic.h> +#include "crc.h" + +struct nouveau_encoder; struct nv50_atom { struct drm_atomic_state state; @@ -115,9 +118,12 @@ struct nv50_head_atom { u8 nhsync:1; u8 nvsync:1; u8 depth:4; + u8 crc_raster:2; u8 bpc; } or; + struct nv50_crc_atom crc; + /* Currently only used for MST */ struct { int pbn; @@ -135,6 +141,7 @@ struct nv50_head_atom { bool ovly:1; bool dither:1; bool procamp:1; + bool crc:1; bool or:1; }; u16 mask; @...

...ne __NV50_KMS_ATOM_H__ #define nv50_atom(p) container_of((p), struct nv50_atom, state) #include <drm/drm_atomic.h> +#include "crc.h" + +struct nouveau_encoder; struct nv50_atom { struct drm_atomic_state state; @@ -115,9 +118,12 @@ struct nv50_head_atom { u8 nhsync:1; u8 nvsync:1; u8 depth:4; + u8 crc_raster:2; u8 bpc; } or; + struct nv50_crc_atom crc; + /* Currently only used for MST */ struct { int pbn; @@ -135,6 +141,7 @@ struct nv50_head_atom { bool ovly:1; bool dither:1; bool procamp:1; + bool crc:1; bool or:1; }; u16 mask; @...

...ne __NV50_KMS_ATOM_H__ #define nv50_atom(p) container_of((p), struct nv50_atom, state) #include <drm/drm_atomic.h> +#include "crc.h" + +struct nouveau_encoder; struct nv50_atom { struct drm_atomic_state state; @@ -115,9 +118,12 @@ struct nv50_head_atom { u8 nhsync:1; u8 nvsync:1; u8 depth:4; + u8 crc_raster:2; u8 bpc; } or; + struct nv50_crc_atom crc; + /* Currently only used for MST */ struct { int pbn; @@ -135,6 +141,7 @@ struct nv50_head_atom { bool ovly:1; bool dither:1; bool procamp:1; + bool crc:1; bool or:1; }; u16 mask; @...

...t fg); void nv_crtc_load_cursor_image(xf86CrtcPtr crtc, CARD8 *image); void nv_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); +void nv_cursor_convert_cursor(uint32_t *src, void *dst, int src_stride, + int dst_stride, int bpp, uint32_t fg, uint32_t bg); /* in nv_dma.c */ void NVSync(ScrnInfoPtr pScrn); -- 1.6.3.3

...ns(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 43df86c38f58..24f7700768da 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -114,6 +114,7 @@ struct nv50_head_atom { u8 nhsync:1; u8 nvsync:1; u8 depth:4; + u8 bpc; } or; /* Currently only used for MST */ diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 6327aaf37c08..93665aecce57 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp...

...67 insertions(+), 17 deletions(-) diff --git a/src/nouveau_exa.c b/src/nouveau_exa.c index 93fc3c5..074a226 100644 --- a/src/nouveau_exa.c +++ b/src/nouveau_exa.c @@ -259,7 +259,11 @@ nouveau_exa_mark_sync(ScreenPtr pScreen) static void nouveau_exa_wait_marker(ScreenPtr pScreen, int marker) { - NVSync(xf86Screens[pScreen->myNum]); + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + NVPtr pNv = NVPTR(pScrn); + + if (!pNv->exa_driver_pixmaps) + NVSync(xf86Screens[pScreen->myNum]); } static Bool @@ -351,17 +355,16 @@ nouveau_exa_modify_pixmap_header(PixmapPtr ppix, int width, int...

Realized when I moved nouveau over to using the atomic DP MST VCPI helpers that I forgot to ensure that we clamp the BPC to 8 to make us less likely to run out of bandwidth on a topology when enabling multiple displays that support >8 BPC - something we want to do until we have support for dynamically selecting the bpc based on the topology's available bandwidth, since userspace isn't

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests that we'll be sending in just a short bit. This additionally adds a feature that Ville Syrj?l? came up with: vblank works. Basically, this is just a generic DRM

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests that we'll be sending in just a short bit. This additionally adds a feature that Ville Syrj?l? came up with: vblank works. Basically, this is just a generic DRM

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up