Displaying 2 results from an estimated 2 matches for "nvsema".
2012 Dec 20
0
reproducible CACHE_ERRORS
...s (with a bit improved logging):
nouveau E[ PFIFO][0000:02:00.0] CACHE_ERROR - ch 6 [glxgears[15559]] subc 0 mthd 0x0060 data 0x8000000f c1p0 0x20000010 HASH_FAILED (unknown bits 0x20000000) c1_hash 0x00000436
What I found so far:
1) It's triggered by setting of NV11_SUBCHAN_DMA_SEMAPHORE to NvSema
(0x8000000f) in nv84_fence_emit. Hw tells us it cannot find ramht entry
for NvSema object (NV04_PFIFO_CACHE1_PULL0 == HASH_FAILED, frequently
unknown 30th bit is set)
2) In 95% cases CACHE_ERRORs are triggered on glxgears channel.
3) RAMHT entry was definitely created and used many times b...
2013 Jul 23
4
[PATCH 1/3] drm/nouveau: fix vblank interrupt being called before event is setup
Sort of fixes mmiotrace for me again, I could sear I sent a similar patch before
the rework to event interface, so I guess it got reintroduced.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com>
---
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 7e3875d..35e526b 100644
---