search for: nvptxregisterinfo

...bc.so.6       0x00007fc73426ca76 __libc_start_main + 370 > 13 llvm-tblgen     0x00000000004071f9 > Stack dump: > 0.    Program arguments: ./llvm-tblgen -gen-tgt-intrinsic NVPTX1.td > Segmentation fault (core dumped) $ llvm-tblgen -gen-tgt-intrinsic NVPTX1.td Included from NVPTX1.td:18: NVPTXRegisterInfo.td:32:14: error: Value list is not of list type foreach i = 0-395 in { ^ Included from NVPTX1.td:18: NVPTXRegisterInfo.td:32:14: error: expected declaration in for foreach i = 0-395 in { ^ > ==== > 2) Second test case: double inclusion of file, that is definitely i...

Dear all, I need your help to understand weird llvm-tblgen behavior. Please take your favourite version of llvm-tblgen and use it in the root directory of the archive attached in both bug reports: http://llvm.org/bugs/show_bug.cgi?id=15188 http://llvm.org/bugs/show_bug.cgi?id=15189 ==== 1) First test case: crashing ==== $ ./llvm-tblgen -gen-tgt-intrinsic NVPTX1.td assert(iid <=

.... It's hard to figure out this in LLVM IR level. 2013/8/7 Justin Holewinski <justin.holewinski at gmail.com> > Is there any way you could approximate the register/instruction usage and > perform live-range analysis in a higher-level LLVM IR pass? I'm not sure > how useful NVPTXRegisterInfo would be anyway. Unlike backends that target > "real" ISAs, these structures do not contain any special properties about > registers or instructions, like cost or scheduling information. Are you > trying to figure out the total number of PTX registers that will be emitted? >...

Is there any way you could approximate the register/instruction usage and perform live-range analysis in a higher-level LLVM IR pass? I'm not sure how useful NVPTXRegisterInfo would be anyway. Unlike backends that target "real" ISAs, these structures do not contain any special properties about registers or instructions, like cost or scheduling information. Are you trying to figure out the total number of PTX registers that will be emitted? On Wed, Aug 7, 20...

...this in LLVM IR level. > > > 2013/8/7 Justin Holewinski <justin.holewinski at gmail.com> > >> Is there any way you could approximate the register/instruction usage and >> perform live-range analysis in a higher-level LLVM IR pass? I'm not sure >> how useful NVPTXRegisterInfo would be anyway. Unlike backends that target >> "real" ISAs, these structures do not contain any special properties about >> registers or instructions, like cost or scheduling information. Are you >> trying to figure out the total number of PTX registers that will be e...

...e/build/./lib/Target/MSP430/InstPrinter/Release+Asserts/MSP430InstPrinter.o differ: byte 8304, line 4 ./lib/Target/NVPTX/Release+Asserts/NVPTXISelDAGToDAG.o ../../recurse2be/build/./lib/Target/NVPTX/Release+Asserts/NVPTXISelDAGToDAG.o differ: byte 112898, line 593 ./lib/Target/NVPTX/Release+Asserts/NVPTXRegisterInfo.o ../../recurse2be/build/./lib/Target/NVPTX/Release+Asserts/NVPTXRegisterInfo.o differ: byte 7339, line 7 ./lib/Target/NVPTX/InstPrinter/Release+Asserts/NVPTXInstPrinter.o ../../recurse2be/build/./lib/Target/NVPTX/InstPrinter/Release+Asserts/NVPTXInstPrinter.o differ: byte 93036, line 145 ./lib/Tar...

OK. I know what you mean......... Simply speaking, I want to do some optimizations for PTX, and the information I need is similar to a register allocator. I know PTX is virtual ISA, but I will use PTX as the input of the simulator, gpgpu-sim, so it makes sense. Whether to insert shared memory is depend on the analysis that needs LiveAnalysis, PTX InstrInfo, PTX RegisterInfo, etc. That's why I