search for: nvmx_msr_read_intercept

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

...> --- xen/arch/x86/hvm/vmx/vvmx.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index cecc72f..879af58 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1815,6 +1815,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) { struct vcpu *v = current; u64 data = 0, host_data = 0; + unsigned int eax, ebx, ecx, edx; int r = 1; if ( !nestedhvm_enabled(v->domain) ) @@ -1925,8 +1926,13 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)...

...gt;nv_vvmcx, VM_EXIT_CONTROLS) & @@ -1371,6 +1372,7 @@ static void virtual_vmexit(struct cpu_user_regs *regs) if ( cpu_has_vmx_virtual_intr_delivery ) nvmx_update_apicv(v); + nvcpu->nv_vmswitch_in_progress = 0; vmreturn(regs, VMSUCCEED); } @@ -1876,6 +1878,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) data = SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | SECONDARY_EXEC_ENABLE_VPID | + SECONDARY_EXEC_UNRESTRICTED_GUEST | SECONDARY_EXEC_ENABLE_EPT;...

...intel.com> --- xen/arch/x86/hvm/vmx/vvmx.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 8e005cd..55781e9 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1334,7 +1334,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) case MSR_IA32_VMX_ENTRY_CTLS: /* bit 0-8, and 12 must be 1 (refer G5 of SDM) */ data = 0x11ff; - data |= VM_ENTRY_IA32E_MODE; data = (data << 32) | data; break; -- 1.7.0.4 _______________________________...

...w_control(struct vcpu *v) nvmx_update_entry_control(v); vmx_update_exception_bitmap(v); nvmx_update_apic_access_address(v); + nvmx_update_virtual_apic_address(v); + nvmx_update_tpr_threshold(v); } static void load_shadow_guest_state(struct vcpu *v) @@ -1371,6 +1404,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) CPU_BASED_ACTIVATE_MSR_BITMAP | CPU_BASED_PAUSE_EXITING | CPU_BASED_RDPMC_EXITING | + CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; data = gen_vmx_msr(data, VMX...

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page