search for: nvmemexec

...hen using the nouveau driver, my screen freezes (and stays frozen) when it starts to more than a minimum amount of work. To fix this, I've been using the nvidia driver with the Preferred Mode set to Prefer Maximum Performance. It looks like equivalent settings in nouveau are NvClkMode and NvMemExec. However, I didn't see any documentation specifying the valid options for these settings? What are the valid options for NvClkMode? What are the valid options for NvMemExec? Thanks. Joseph D. Wagner

...x ef91b6e..e5d12c2 100644 --- a/nvkm/subdev/fb/ramnv50.c +++ b/nvkm/subdev/fb/ramnv50.c @@ -211,7 +211,7 @@ nv50_ram_prog(struct nouveau_fb *pfb) struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; - ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", false)); + ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } diff --git a/nvkm/subdev/fb/ramnva3.c b/nvkm/subdev/fb/ramnva3.c index 6eb97f1..8076fb1 100644 --- a/nvkm/subdev/fb/ramnva3.c +++ b/nvkm/subdev/fb/ramnva3.c @@ -309,7 +309,7 @@ nva3_r...

...ouveau driver, my screen freezes (and stays frozen) when it > starts to more than a minimum amount of work. To fix this, I've been using > the nvidia driver with the Preferred Mode set to Prefer Maximum Performance. > > It looks like equivalent settings in nouveau are NvClkMode and NvMemExec. > However, I didn't see any documentation specifying the valid options for > these settings? > > What are the valid options for NvClkMode? This takes the decimal (!) value of the pstate you want to clock to on boot. The valid pstates are defined by your VBIOS, and are visible in /...

...> when it >> starts to more than a minimum amount of work. To fix this, I've been >> using >> the nvidia driver with the Preferred Mode set to Prefer Maximum >> Performance. >> >> It looks like equivalent settings in nouveau are NvClkMode and >> NvMemExec. >> However, I didn't see any documentation specifying the valid options >> for >> these settings? >> >> What are the valid options for NvClkMode? > > This takes the decimal (!) value of the pstate you want to clock to on > boot. The valid pstates are d...

...;> > with engine clocks on some boards that I'm aware of, so it's not just a >> > memory reclocking worry here. >> > >> > That said, it has a good chance of working for some people. So. >> > Thoughts? >> > I'm also talking making "NvMemExec" default on here too. Again, causing >> > a >> > fuck-up will still require direct user action. >> > >> > For the rest (Hm, except maybe nv40, a lot will probably be ok..) >> > There's >> > *very* little chance memory reclocking will w...

...lready, there's potentially some severe issues even > with engine clocks on some boards that I'm aware of, so it's not just a > memory reclocking worry here. > > That said, it has a good chance of working for some people. So. Thoughts? > I'm also talking making "NvMemExec" default on here too. Again, causing a > fuck-up will still require direct user action. > > For the rest (Hm, except maybe nv40, a lot will probably be ok..) There's > *very* little chance memory reclocking will work, even on the systems where > it used to. The code is far...

...bdev/fb/ramgf100.c +++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -409,7 +409,7 @@ gf100_ram_prog(struct nvkm_ram *base) { struct gf100_ram *ram = gf100_ram(base); struct nvkm_device *device = ram->base.fb->subdev.device; - ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); + ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", false)); return 0; } -- 2.5.3

...tially some severe issues even > > with engine clocks on some boards that I'm aware of, so it's not just a > > memory reclocking worry here. > > > > That said, it has a good chance of working for some people. So. Thoughts? > > I'm also talking making "NvMemExec" default on here too. Again, causing a > > fuck-up will still require direct user action. > > > > For the rest (Hm, except maybe nv40, a lot will probably be ok..) There's > > *very* little chance memory reclocking will work, even on the systems where > > it...

Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> --- drm/nouveau/include/nvkm/subdev/ibus.h | 1 + drm/nouveau/nvkm/engine/device/base.c | 4 +-- drm/nouveau/nvkm/subdev/ibus/Kbuild | 1 + drm/nouveau/nvkm/subdev/ib...

Adds a NvReclock boolean option to allow the user to enable (or disable) reclocking. All chipsets default to off, except NVAA/NVAC, which are reportedly complete. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Ben, I know you've been saying that reclocking is in a pretty bad state, but I do think that there are going to be groups of people for whom the current code can work

https://bugs.freedesktop.org/show_bug.cgi?id=71994 Priority: medium Bug ID: 71994 Assignee: nouveau at lists.freedesktop.org Summary: Can't set performance level on Fermi card, Linux 3.13 Severity: normal Classification: Unclassified OS: All Reporter: anakin.cs at gmail.com Hardware: Other

https://bugs.freedesktop.org/show_bug.cgi?id=75094 Priority: medium Bug ID: 75094 Assignee: nouveau at lists.freedesktop.org Summary: NV92 is faster and runs games fine than NVE6, why? Severity: normal Classification: Unclassified OS: All Reporter: fast.rizwaan at gmail.com Hardware: Other

...boards where it is a known problem. + * + * * NvGrUseFW (boolean): Load firmware for PGRAPH (valid on the NVC0, NVE0, + * and NV110 families); defaults to false. + * + * * NvI2C (boolean): Use the nouveau-internal I2C bus driver rather than the + * I2C bit-adapters; defaults to false. + * + * * NvMemExec (boolean): Perform memory reclocking; defaults to true. + * + * * NvMSI (boolean): Use MSI interrupts; defaults to true on chipsets that + * support it.. + * + * * NvMXMDCB (boolean): Sanitize DCB outputs from the VBIOS; defaults to true. + * + * * NvPCIE (boolean): Whether to use the PCI-E GART...

...decent number of cases already, there's potentially some severe issues even with engine clocks on some boards that I'm aware of, so it's not just a memory reclocking worry here. That said, it has a good chance of working for some people. So. Thoughts? I'm also talking making "NvMemExec" default on here too. Again, causing a fuck-up will still require direct user action. For the rest (Hm, except maybe nv40, a lot will probably be ok..) There's *very* little chance memory reclocking will work, even on the systems where it used to. The code is far less complete, as it was...

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

...boards where it is a known problem. + * + * * NvGrUseFW (boolean): Load firmware for PGRAPH (valid on the NVC0, NVE0, + * and NV110 families); defaults to false. + * + * * NvI2C (boolean): Use the nouveau-internal I2C bus driver rather than the + * I2C bit-adapters; defaults to false. + * + * * NvMemExec (boolean): Perform memory reclocking; defaults to true. + * + * * NvMSI (boolean): Use MSI interrupts; defaults to true on chipsets that + * support it.. + * + * * NvMXMDCB (boolean): Sanitize DCB outputs from the VBIOS; defaults to true. + * + * * NvPCIE (boolean): Whether to use the PCI-E GART...

...+ * > + * * NvGrUseFW (boolean): Load firmware for PGRAPH (valid on the NVC0, NVE0, > + * and NV110 families); defaults to false. > + * > + * * NvI2C (boolean): Use the nouveau-internal I2C bus driver rather than the > + * I2C bit-adapters; defaults to false. > + * > + * * NvMemExec (boolean): Perform memory reclocking; defaults to true. > + * > + * * NvMSI (boolean): Use MSI interrupts; defaults to true on chipsets that > + * support it.. > + * > + * * NvMXMDCB (boolean): Sanitize DCB outputs from the VBIOS; defaults to true. > + * > + * * NvPCIE (boole...

...vice(pfb); + struct nva3_ramfuc *fuc = &ram->fuc; + u32 *result, r1700; + int ret, i; + struct nvbios_M0205T M0205T = { 0 }; + u8 ver, hdr, cnt, len, snr, ssz; + unsigned int clk_current; + unsigned long flags; + unsigned long *f = &flags; + + if (nouveau_boolopt(device->cfgopt, "NvMemExec", true) != true) + return -ENOSYS; + + /* XXX: Multiple partitions? */ + result = kmalloc(64 * sizeof(u32), GFP_KERNEL); + if (!result) + return -ENOMEM; + + train->state = NVA3_TRAIN_EXEC; + + /* Clock speeds for training and back */ + nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &...