search for: nvkm_warn

...c index 814daf35e21f..f865d2a3e184 100644 --- a/drm/nouveau/nvkm/engine/sec2/base.c +++ b/drm/nouveau/nvkm/engine/sec2/base.c @@ -59,6 +59,13 @@ static void nvkm_sec2_recv(struct work_struct *work) { struct nvkm_sec2 *sec2 = container_of(work, typeof(*sec2), work); + + if (!sec2->queue) { + nvkm_warn(&sec2->engine.subdev, + "recv function called while no firmware set!\n"); + return; + } + nvkm_msgqueue_recv(sec2->queue); } diff --git a/drm/nouveau/nvkm/falcon/msgqueue.c b/drm/nouveau/nvkm/falcon/msgqueue.c index 18111d66d3d4..07e752603bae 100644 --- a/drm/nouveau/n...

...the streaming DMA mask here as well. + */ + dma_set_mask(device->dev, DMA_BIT_MASK(device->mmu->dma_bits)); + + fb->r100c08 = dma_map_page(device->dev, fb->r100c08_page, 0, + PAGE_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(device->dev, fb->r100c08)) { + nvkm_warn(&fb->base.subdev, + "dma_map_page() failed on 100c08 page\n"); + } + } + /* Not a clue what this is exactly. Without pointing it at a * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) * cause IOMMU "read from address 0" errors (rh#561267) */...

...44 --- a/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -129,9 +129,7 @@ gf100_ltc_invalidate(struct nvkm_ltc *ltc) s64 taken; nvkm_wr32(device, 0x70004, 0x00000001); - taken = nvkm_wait_msec(device, 2, 0x70004, 0x00000003, 0x00000000); - if (taken < 0) - nvkm_warn(&ltc->subdev, "LTC invalidate timeout\n"); + taken = nvkm_wait_msec(device, 2000, 0x70004, 0x00000003, 0x00000000); if (taken > 0) nvkm_debug(&ltc->subdev, "LTC invalidate took %lld ns\n", taken); @@ -144,9 +142,7 @@ gf100_ltc_flush(struct nvkm_ltc *ltc)...

...vkm_msec(device, 2000, + + /* Test PLL lock */ + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); + if (nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; - ); - nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); + ) < 0) { + nvkm_warn(&clk->base.subdev, + "Could not lock PLL %d", idx); + } + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); + + /* Enable sync mode */ + nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004); } } } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104...

...struct nvbios_power_budget *budget) { - struct nvkm_subdev *subdev = &bios->subdev; u8 ver, hdr, cnt, len, cap_entry; u32 header; @@ -82,7 +81,7 @@ nvbios_power_budget_header(struct nvkm_bios *bios, } if (cap_entry >= cnt && cap_entry != 0xff) { - nvkm_warn(subdev, + nvkm_warn(&bios->subdev, "invalid cap_entry in power budget table found\n"); budget->cap_entry = 0xff; return -EINVAL; -- 2.40.0

...); struct nvkm_device *device = fb->base.subdev.device; + if (!fb->r100c08) { + dma_addr_t addr = dma_map_page(device->dev, fb->r100c08_page, 0, + PAGE_SIZE, DMA_BIDIRECTIONAL); + if (!dma_mapping_error(device->dev, addr)) { + fb->r100c08 = addr; + } else { + nvkm_warn(&fb->base.subdev, + "dma_map_page() failed on 100c08 page\n"); + } + } + /* Not a clue what this is exactly. Without pointing it at a * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) * cause IOMMU "read from address 0" errors (rh#561267) */...

Due to the lack of implicit synchronization between CPU and GPU on Tegra systems (like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B relied on the slow, legacy PRAMIN so that CPU accesses used the same path as GPU, making sure we see the same data on both ends. The recent Nouveau refactoring introduced acquire/release functions on instmem that help us understand the

...int nvkm_clk_tstate(struct nvkm_clk *clk, u8 temp) { + struct nvkm_subdev *subdev = &clk->subdev; if (clk->temp == temp) return 0; clk->temp = temp; + if (clk->max_temp && clk->relax_temp) { + if (!clk->throttled && temp > clk->max_temp) { + nvkm_warn(subdev, + "temperature (%d C) hit the 'downclock' " + "threshold\n", + temp); + clk->throttled = true; + } else if (clk->throttled && temp < clk->relax_temp) { + nvkm_warn(subdev, + "temperature (%d C) went below the &quo...

...*/ + dma_addr_t addr; + + dma_set_mask(device->dev, DMA_BIT_MASK(device->mmu->dma_bits)); + + addr = dma_map_page(device->dev, fb->r100c08_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (!dma_mapping_error(device->dev, addr)) { + fb->r100c08 = addr; + } else { + nvkm_warn(&fb->base.subdev, + "dma_map_page() failed on 100c08 page\n"); + } + } + /* Not a clue what this is exactly. Without pointing it at a * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) * cause IOMMU "read from address 0" errors (rh#561267) */...

This v4 is now a 3 piece series, after Alexandre pointed out that both GF 100 and NV50 are affected by the same issue, and that a related issue has been solved already for Tegra in commit 9d0394c6bed5 ("drm/nouveau/instmem/gk20a: set DMA mask early"). The issue that this series addresses is the fact that the Nouveau driver invokes the DMA API before setting the DMA mask. In both cases

...= gk20a_clk_ctor(device, index, &gm20b_clk, clk_params, &clk->base); if (ret) - return ret; + goto out_free; /* * NAPLL can only work with max_u, clamp the m range so @@ -1067,8 +1067,8 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) nvkm_warn(subdev, "no fused calibration parameters\n"); ret = gm20b_clk_init_safe_fmax(clk); - if (ret) - return ret; - return 0; +out_free: + kfree(clk); + return ret; } -- 2.17.1

Following a series of three patches, two of which have been sitting in my tree for a while, the third is the result of some inspection of an NV134 BIOS that seems to use the 0xaf upcode to upload training patterns. Please test! Roy Ps. Sorry they come from yet another e-mail address. My previous provider, eclipso, actively blocks users of git send-email. Inquiries fall on deaf ears, hence I

...the streaming DMA mask here as well. + */ + dma_set_mask(device->dev, DMA_BIT_MASK(device->mmu->dma_bits)); + + fb->r100c08 = dma_map_page(device->dev, fb->r100c08_page, 0, + PAGE_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(device->dev, fb->r100c08)) { + nvkm_warn(&fb->base.subdev, + "dma_map_page() failed on 100c08 page\n"); + } + } + /* Not a clue what this is exactly. Without pointing it at a * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) * cause IOMMU "read from address 0" errors (rh#561267) */...

...nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_SEC); + else + i2c_bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI); + if (!i2c_bus) + return NULL; + + addr = extdev.addr >> 1; + if (!nvkm_iccsense_validate_device(&i2c_bus->i2c, addr, + extdev.type)) { + iccsense->data_valid = false; + nvkm_warn(subdev, "found invalid sensor id: %i, power reading" + "might be invalid\n", id); + return NULL; + } + + sensor = kmalloc(sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return NULL; + + list_add_tail(&sensor->head, &iccsense->sensors); + sensor->id = id; +...

...r / 3)); > @@ -150,12 +147,6 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) > nvkm_trace(subdev, "utilization = %d %%, avg_load = %d %%\n", > utilization, data->avg_load); > > - ret = gk20a_pmu_dvfs_get_cur_state(pmu, &state); > - if (ret) { > - nvkm_warn(subdev, "failed to get current state\n"); > - goto resched; > - } > - > if (gk20a_pmu_dvfs_get_target_state(pmu, &state, data->avg_load)) { > nvkm_trace(subdev, "set new state to %d\n", state); > gk20a_pmu_dvfs_target(pmu, &state);

...gt; + case 0x20: > + cap_entry = nvbios_rd08(bios, header + 0x9); > + break; > + case 0x30: > + cap_entry = nvbios_rd08(bios, header + 0xa); > + break; > + default: > + cap_entry = 0xff; > + } > + > + if (cap_entry >= cnt && cap_entry != 0xff) { > + nvkm_warn(subdev, > + "invalid cap_entry in power budget table found\n"); > + budget->cap_entry = 0xff; > + return -EINVAL; > + } > + > + budget->cap_entry = cap_entry; > + return 0; > +} > + > +int > +nvbios_power_budget_entry(struct nvkm_bios *b...

...the potential 2s timeout values across the driver in general, to avoid things hanging for a long time when the GPU craps itself :) > + if ((nvkm_rd32(device, 0x70004) & 0x00000003) == 0x00000000) > + break; > + )) < 0) > + nvkm_warn(&ltc->subdev, "L2 invalidate timeout\n"); > + > + if (taken > 0) > + nvkm_debug(&ltc->subdev, "LTC invalidate took %lld ns\n", taken); > +} > + > +void > +gf100_ltc_flush(struct nvkm_ltc *ltc) > +{ > + struct...

...ry = nvbios_rd08(bios, header + 0x9); > + break; > + default: > + cap_entry = 0; Are you sure about this? How about setting it to 0xff instead? > + } > + > + if (cap_entry < cnt) > + budget->cap_entry = cap_entry; > + else { > + if (cap_entry != 0xff) > + nvkm_warn(subdev, > + "invalid cap_entry in power budget table found\n"); > + budget->cap_entry = 0xff; > + } > + > + for (i = 0; i < cnt; ++i) { > + u32 entry_offset = header + hdr + i * len; > + struct nvbios_power_budget_entry *entry = &budget->entries[i...

...= gf100_ram(base); - struct nvkm_device *device = ram->base.fb->subdev.device; - int i; + struct nvkm_subdev *subdev = &ram->fb->subdev; + struct nvkm_device *device = subdev->device; + int i, j; - switch (ram->base.type) { + if ((train->mask & 0x03d3) != 0x03d3) { + nvkm_warn(subdev, "missing link training data\n"); + return -EINVAL; + } + + for (i = 0; i < 0x30; i++) { + for (j = 0; j < 8; j += 4) { + nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8)); + nvkm_wr32(device, 0x10f920 + j, 0x00000000 | + train->type08.data[i] <...

The power sensors can be configured to sample the readout values over time. Nvidia does this too, so nouveau should probably do that too. Karol Herbst (4): iccsense: remove read function iccsense: convert to linked list iccsense: split sensor into own struct iccsense: configure sensors like nvidia does drm/nouveau/include/nvkm/subdev/iccsense.h | 6 +- drm/nouveau/nouveau_hwmon.c