search for: nvkm_vm_new

...m for inst blk*/ + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, &pmuvm->mem); + if (ret) + return ret; + + /* mem for pgd*/ + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, &pmuvm->pgd); + if (ret) + return ret; + + /*allocate virtual memory range*/ + ret = nvkm_vm_new(device, 0, pmu_area_len, 0, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_PMU]); + + /* update VM with pgd */ + ret = nvkm_vm_ref(vm, &pmuvm->vm, pmuvm->pgd); + if (ret) + return ret; + + /*update pgd in inst blk */ + nv_wo32(pmuvm->mem, 0x0200, lo...

...uobj_new(nv_object(ppmu), NULL, 0x1000, 0, 0, + &ppmuvm->mem); + if (ret) + goto instblk_alloc_err; + + /* mem for pgd*/ + ret = nvkm_gpuobj_new(nv_object(ppmu), NULL, 0x8000, 0, 0, + &ppmuvm->pgd); + if (ret) + goto pgd_alloc_err; + + /*allocate virtual memory range*/ + ret = nvkm_vm_new(device, 0, pmu_area_len, 0, &vm); + if (ret) + goto fw_alloc_err; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_PMU]); + /*update VM with pgd */ + + ret = nvkm_vm_ref(vm, &ppmuvm->vm, ppmuvm->pgd); + if (ret) + goto fw_alloc_err; + + /*update pgd in inst blk */ + nv_wo32(ppmuvm-&gt...

...>> + >> + /* mem for pgd*/ >> + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, >> &pmuvm->pgd); >> + if (ret) >> + return ret; >> + >> + /*allocate virtual memory range*/ >> + ret = nvkm_vm_new(device, 0, pmu_area_len, 0, &vm); >> + if (ret) >> + return ret; >> + >> + atomic_inc(&vm->engref[NVDEV_SUBDEV_PMU]); >> + >> + /* update VM with pgd */ >> + ret = nvkm_vm_ref(vm, &pmuvm->vm, pmuvm-&gt...

...onst u64 vm_area_len = 600 * 1024; + int ret; + + /* Allocate instance block and VM */ + ret = nvkm_gpuobj_new(device, 0x1000, 0, true, NULL, &gsb->inst); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x8000, 0, true, NULL, &gsb->pgd); + if (ret) + return ret; + + ret = nvkm_vm_new(device, 0, vm_area_len, 0, NULL, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVKM_SUBDEV_PMU]); + + ret = nvkm_vm_ref(vm, &gsb->vm, gsb->pgd); + nvkm_vm_ref(NULL, &vm, NULL); + if (ret) + return ret; + + nvkm_kmap(gsb->inst); + nvkm_wo32(gsb->inst, 0x2...

...+ > + /* mem for pgd*/ > + ret = nvkm_gpuobj_new(nv_object(ppmu), NULL, 0x8000, 0, 0, > + &ppmuvm->pgd); > + if (ret) > + goto pgd_alloc_err; > + > + /*allocate virtual memory range*/ > + ret = nvkm_vm_new(device, 0, pmu_area_len, 0, &vm); > + if (ret) > + goto virt_alloc_err; > + > + atomic_inc(&vm->engref[NVDEV_SUBDEV_PMU]); > + /*update VM with pgd */ > + > + ret = nvkm_vm_ref(vm, &ppmuvm->vm, ppmuvm->pgd); > +...

...uobj_new(nv_object(ppmu), NULL, 0x1000, 0, 0, + &ppmuvm->mem); + if (ret) + goto instblk_alloc_err; + + /* mem for pgd*/ + ret = nvkm_gpuobj_new(nv_object(ppmu), NULL, 0x8000, 0, 0, + &ppmuvm->pgd); + if (ret) + goto pgd_alloc_err; + + /*allocate virtual memory range*/ + ret = nvkm_vm_new(device, 0, pmu_area_len, 0, &vm); + if (ret) + goto virt_alloc_err; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_PMU]); + /*update VM with pgd */ + + ret = nvkm_vm_ref(vm, &ppmuvm->vm, ppmuvm->pgd); + if (ret) + goto virt_alloc_err; + + /*update pgd in inst blk */ + nv_wo32(ppmuvm...

...+ > + /* mem for pgd*/ > + ret = nvkm_gpuobj_new(nv_object(ppmu), NULL, 0x8000, 0, 0, > + &ppmuvm->pgd); > + if (ret) > + goto pgd_alloc_err; > + > + /*allocate virtual memory range*/ > + ret = nvkm_vm_new(device, 0, pmu_area_len, 0, &vm); > + if (ret) > + goto virt_alloc_err; > + > + atomic_inc(&vm->engref[NVDEV_SUBDEV_PMU]); > + /*update VM with pgd */ > + > + ret = nvkm_vm_ref(vm, &ppmuvm->vm, ppmuvm->pgd); > +...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a