search for: nvkm_vm

Hi, Generally the the imported buffers which has memory type TTM_PL_TT are mapped as small pages probably due to lack of big page allocation. But the platform device which also use memory type TTM_PL_TT, like GK20A, can *allocate* big page though the IOMMU hardware inside the SoC. This is a try to map the imported buffers as big pages in GMMU by the platform IOMMU. With some preparation work to

...+struct gk20a_mmu_priv { > + struct nvkm_mmu base; > +}; > + > +struct gk20a_mmu_iommu_mapping { > + struct nvkm_mm_node *node; > + u64 iova; > +}; > + > +extern const u8 gf100_pte_storage_type_map[256]; > + > +static void > +gk20a_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, > + struct nvkm_mem *mem, u32 pte, u64 list) > +{ > + u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; > + u64 phys; > + > + pte <<= 3; > + phys = gf100_vm_addr(vma, list, mem->memt...

...rtions(+), 7 deletions(-) > > diff --git a/drm/nouveau/include/nvkm/subdev/mmu.h b/drm/nouveau/include/nvkm/subdev/mmu.h > index 3a5368776c31..3230d31a7971 100644 > --- a/drm/nouveau/include/nvkm/subdev/mmu.h > +++ b/drm/nouveau/include/nvkm/subdev/mmu.h > @@ -22,6 +22,8 @@ struct nvkm_vma { > struct nvkm_mm_node *node; > u64 offset; > u32 access; > + struct list_head bp; > + bool has_iommu_bp; Whether a chunk of memory is mapped through the IOMMU can be tested by checking if the IOMMU bit is set in the address recorded in the PTE....

...6KB, increase the size of the buffer to the next multiple of 128K and use big pages" would probably yield better results. > } > > nouveau_bo_fixup_align(nvbo, flags, &align, &size); > @@ -1641,6 +1646,10 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm, > (nvbo->bo.mem.mem_type == TTM_PL_VRAM || > nvbo->page_shift != vma->vm->mmu->lpg_shift)) > nvkm_vm_map(vma, nvbo->bo.mem.mm_node); > + else if (nvbo->bo.mem.mem_type == TTM_PL_TT && > + v...

...E = 0, + GK20A_PMU_DMAIDX_VIRT = 1, + GK20A_PMU_DMAIDX_PHYS_VID = 2, + GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3, + GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4, + GK20A_PMU_DMAIDX_RSVD = 5, + GK20A_PMU_DMAIDX_PELPG = 6, + GK20A_PMU_DMAIDX_END = 7 +}; + +struct pmu_buf_desc { + struct nvkm_gpuobj *obj; + struct nvkm_vma vma; + size_t size; +}; + +struct nvkm_pmu_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +/*Choices for pmu_state*/ +enum { + PMU_STATE_OFF, /*0 PMU is off */ + PMU_STATE_STARTING, /*1 PMU is on, but not booted */ + PMU_STATE_INIT_...

...E = 0, + GK20A_PMU_DMAIDX_VIRT = 1, + GK20A_PMU_DMAIDX_PHYS_VID = 2, + GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3, + GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4, + GK20A_PMU_DMAIDX_RSVD = 5, + GK20A_PMU_DMAIDX_PELPG = 6, + GK20A_PMU_DMAIDX_END = 7 +}; + +struct pmu_buf_desc { + struct nvkm_gpuobj *obj; + struct nvkm_vma vma; + size_t size; +}; + +struct nvkm_pmu_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +/* Choices for pmu_state */ +enum { + PMU_STATE_OFF, /*0 PMU is off */ + PMU_STATE_STARTING, /*1 PMU is on, but not booted */ + PMU_STATE_INI...

...S_SYS_NCOH = 4, >> + GK20A_PMU_DMAIDX_RSVD = 5, >> + GK20A_PMU_DMAIDX_PELPG = 6, >> + GK20A_PMU_DMAIDX_END = 7 >> +}; >> + >> +struct pmu_buf_desc { >> + struct nvkm_gpuobj *obj; >> + struct nvkm_vma vma; >> + size_t size; >> +}; >> + >> +struct nvkm_pmu_priv_vm { >> + struct nvkm_gpuobj *mem; >> + struct nvkm_gpuobj *pgd; >> + struct nvkm_vm *vm; >> +}; >> + >> +/*Choices for pmu_state*/ >> +enum { >&...

...rtual address */ + nvkm_wr32(device, base + 0x104, virt_addr); + + return 0; +} + +/** + * gm200_secboot_run_hs_blob() - run the given high-secure blob + */ +static int +gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, + struct gm200_flcn_bl_desc *desc) +{ + struct nvkm_vma vma; + u64 vma_addr; + const u32 bl_desc_size = gsb->func->bl_desc_size; + u8 bl_desc[bl_desc_size]; + int ret; + + /* Map the HS firmware so the HS bootloader can see it */ + ret = nvkm_gpuobj_map(blob, gsb->vm, NV_MEM_ACCESS_RW, &vma); + if (ret) + return ret; + + /* Add the mappin...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

.../drm/nouveau/include/nvkm/subdev/pmu.h @@ -1,7 +1,20 @@ #ifndef __NVKM_PMU_H__ #define __NVKM_PMU_H__ #include <core/subdev.h> +#include <core/device.h> +#include <subdev/mmu.h> +#include <linux/debugfs.h> +struct pmu_buf_desc { + struct nvkm_gpuobj *pmubufobj; + struct nvkm_vma pmubufvma; + size_t size; +}; +struct pmu_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; struct nvkm_pmu { struct nvkm_subdev base; @@ -20,9 +33,20 @@ struct nvkm_pmu { u32 message; u32 data[2]; } recv; - + wait_queue_head_t init_wq; + bool g...

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

...#ifndef __NVKM_PMU_H__ > #define __NVKM_PMU_H__ > #include <core/subdev.h> > +#include <core/device.h> > +#include <subdev/mmu.h> > +#include <linux/debugfs.h> > > +struct pmu_buf_desc { > + struct nvkm_gpuobj *pmubufobj; > + struct nvkm_vma pmubufvma; > + size_t size; > +}; > +struct pmu_priv_vm { > + struct nvkm_gpuobj *mem; > + struct nvkm_gpuobj *pgd; > + struct nvkm_vm *vm; > +}; > struct nvkm_pmu { > struct nvkm_subdev base; > > @@ -20,9 +33,20 @@ struct nvkm_pmu...

...#ifndef __NVKM_PMU_H__ > #define __NVKM_PMU_H__ > #include <core/subdev.h> > +#include <core/device.h> > +#include <subdev/mmu.h> > +#include <linux/debugfs.h> > > +struct pmu_buf_desc { > + struct nvkm_gpuobj *pmubufobj; > + struct nvkm_vma pmubufvma; > + size_t size; > +}; > +struct pmu_priv_vm { > + struct nvkm_gpuobj *mem; > + struct nvkm_gpuobj *pgd; > + struct nvkm_vm *vm; > +}; > struct nvkm_pmu { > struct nvkm_subdev base; > > @@ -20,9 +33,20 @@ struct nvkm_pmu...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

...atches have already been posted on mesa mailing list. They are two aspect that need to sorted before this can be considered ready. First we want to decide how to update GPU page table from HMM. In this patchset i added new methods to vmm to allow GPU page table to be updated without nvkm_memory or nvkm_vma object (see patch 7 and 8 special mapping method for HMM). It just take an array of pages and flags. It allow for both system and device private memory to be interleaved. The second aspect is how to create a HMM enabled channel. Channel is a term use for NVidia GPU command queue, each process usi...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,