search for: nvkm_subdev_fini

....669153fba 100644 --- a/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -292,8 +292,12 @@ gk104_fifo_recover_work(struct work_struct *w) for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { if ((engine = fifo->engine[engn].engine)) { - nvkm_subdev_fini(&engine->subdev, false); - WARN_ON(nvkm_subdev_init(&engine->subdev)); + mutex_lock(&engine->subdev.mutex); + if (engine->usecount) { + nvkm_subdev_fini(&engine->subdev, false); + WARN_ON(nvkm_subdev_init(&engine->subdev)); + } + mutex_unlock(&a...

Changes since last sent: * add a patch to set the device into DRM_SWITCH_POWER_CHANGING state (can be dropped actually, I thought I was needing it, came up with a different approach and forgot to delete it, doesn't hurt though) * expose information about runtime suspending to nvkm so that we can run the pcie workaround only on runtime suspend Karol Herbst (8): pci: disable ASPM

nvkm_mm_fini() was not called when exiting the driver, resulting in a memory leak. Fix this. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nouveau_platform.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drm/nouveau/nouveau_platform.c b/drm/nouveau/nouveau_platform.c index 3691982452a9..f83aa12ee5c6 100644 --- a/drm/nouveau/nouveau_platform.c +++

..., 0x1000000, 0x1000000); + } else { + nv_debug(priv, "disable pmu irq\n"); + nv_mask(pmc, 0x00000640, 0x1000000, 0x00000000); + nv_mask(pmc, 0x00000644, 0x1000000, 0x00000000); + nv_wr32(priv, 0x0010a014, 0xff); + } - nvkm_timer_alarm_cancel(priv, &priv->alarm); +} - return nvkm_subdev_fini(&pmu->base, suspend); +static int +gk20a_pmu_idle(struct gk20a_pmu_priv *priv) +{ + if (!nv_wait(priv, 0x0010a04c, 0x0000ffff, 0x00000000)) { + nv_error(priv, "timeout waiting pmu idle\n"); + return -EBUSY; + } + + return 0; +} + +static int +gk20a_pmu_enable(struct gk20a_pmu_pri...

...*)object; int ret; - ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); - if (ret && suspend) - return ret; + if (pfb->ram) { + ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); + if (ret && suspend) + return ret; + } return nvkm_subdev_fini(&pfb->base, suspend); } @@ -72,9 +74,11 @@ _nvkm_fb_init(struct nvkm_object *object) if (ret) return ret; - ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); - if (ret) - return ret; + if (pfb->ram) { + ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));...

...*)object; int ret; - ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); - if (ret && suspend) - return ret; + if (pfb->ram) { + ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); + if (ret && suspend) + return ret; + } return nvkm_subdev_fini(&pfb->base, suspend); } @@ -72,9 +74,11 @@ _nvkm_fb_init(struct nvkm_object *object) if (ret) return ret; - ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); - if (ret) - return ret; + if (pfb->ram) { + ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));...

...*)object; int ret; - ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); - if (ret && suspend) - return ret; + if (pfb->ram) { + ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); + if (ret && suspend) + return ret; + } return nvkm_subdev_fini(&pfb->base, suspend); } @@ -72,9 +74,11 @@ _nvkm_fb_init(struct nvkm_object *object) if (ret) return ret; - ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); - if (ret) - return ret; + if (pfb->ram) { + ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));...

..., 0x1000000, 0x00000000); >> + nv_mask(pmc, 0x00000644, 0x1000000, 0x00000000); >> + nv_wr32(priv, 0x0010a014, 0xff); >> + } >> >> - nvkm_timer_alarm_cancel(priv, &priv->alarm); >> +} >> >> - return nvkm_subdev_fini(&pmu->base, suspend); >> +static int >> +gk20a_pmu_idle(struct gk20a_pmu_priv *priv) >> +{ >> + if (!nv_wait(priv, 0x0010a04c, 0x0000ffff, 0x00000000)) { >> + nv_error(priv, "timeout waiting pmu idle\n"); >> + re...

https://bugs.freedesktop.org/show_bug.cgi?id=92077 Bug ID: 92077 Summary: nouveau graphics freeze when using KDE Plasma 5; PGR engine fault Product: Mesa Version: 10.3 Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component:

...p; suspend) > - return ret; > + if (pfb->ram) { > + ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); > + if (ret && suspend) > + return ret; > + } > > return nvkm_subdev_fini(&pfb->base, suspend); > } > @@ -72,9 +74,11 @@ _nvkm_fb_init(struct nvkm_object *object) > if (ret) > return ret; > > - ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); > - if (ret) > - return ret; >...

Currently, enabling SG_DEBUG in the kernel will cause nouveau to hit a BUG() on startup: kernel BUG at include/linux/scatterlist.h:187! invalid opcode: 0000 [#1] PREEMPT SMP NOPTI CPU: 7 PID: 930 Comm: (udev-worker) Not tainted 6.9.0-rc3Lyude-Test+ #30 Hardware name: MSI MS-7A39/A320M GAMING PRO (MS-7A39), BIOS 1.I0 01/22/2019 RIP: 0010:sg_init_one+0x85/0xa0 Code: 69 88 32 01 83 e1 03

https://bugs.freedesktop.org/show_bug.cgi?id=69882 Priority: medium Bug ID: 69882 Assignee: nouveau at lists.freedesktop.org Summary: [NVE6] GPU lockups QA Contact: xorg-team at lists.x.org Severity: critical Classification: Unclassified OS: Linux (All) Reporter: pastas4 at gmail.com Hardware:

..., bool suspend) { struct nvkm_pmu *pmu = (void *)object; - struct gk20a_pmu_priv *priv = (void *)pmu; - + struct gk20a_pmu_priv *priv = to_gk20a_priv(pmu); + nv_wr32(pmu, 0x10a014, 0x00000060); + flush_work(&pmu->recv.work); nvkm_timer_alarm_cancel(priv, &priv->alarm); return nvkm_subdev_fini(&pmu->base, suspend); } static int +gk20a_pmu_enable_hw(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc, + bool enable) +{ + if (enable) { + nv_mask(pmc, 0x000200, 0x00002000, 0x00002000); + nv_rd32(pmc, 0x00000200); + if (nv_wait(ppmu, 0x0010a10c, 0x00000006, 0x00000000)) + return 0;...

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

...; struct nvkm_pmu *pmu = (void *)object; > struct gk20a_pmu_priv *priv = (void *)pmu; > - > + nv_wr32(pmu, 0x10a014, 0x00000060); > + flush_work(&pmu->recv.work); > nvkm_timer_alarm_cancel(priv, &priv->alarm); > > return nvkm_subdev_fini(&pmu->base, suspend); > } > +static bool find_hex_in_string(char *strings, u32 *hex_pos) > +{ > + u32 i = 0, j = strlen(strings); > + for (; i < j; i++) { > + if (strings[i] == '%') > + if (strings[i + 1] == ...

...233,145 @@ gk20a_pmu_fini(struct nvkm_object *object, bool suspend) { struct nvkm_pmu *pmu = (void *)object; struct gk20a_pmu_priv *priv = (void *)pmu; - + nv_wr32(pmu, 0x10a014, 0x00000060); + flush_work(&pmu->recv.work); nvkm_timer_alarm_cancel(priv, &priv->alarm); return nvkm_subdev_fini(&pmu->base, suspend); } +static bool find_hex_in_string(char *strings, u32 *hex_pos) +{ + u32 i = 0, j = strlen(strings); + for (; i < j; i++) { + if (strings[i] == '%') + if (strings[i + 1] == 'x' || strings[i + 1] == 'X') { + *hex_pos = i; + return true...