search for: nvkm_secboot_falcon_run

...diff --git a/drm/nouveau/nvkm/subdev/secboot/base.c b/drm/nouveau/nvkm/subdev/secboot/base.c index 520facf9bc07..a4f314803137 100644 --- a/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drm/nouveau/nvkm/subdev/secboot/base.c @@ -135,7 +135,8 @@ nvkm_secboot_falcon_reset(struct nvkm_secboot *sb) int nvkm_secboot_falcon_run(struct nvkm_secboot *sb) { - struct nvkm_device *device = sb->subdev.device; + struct nvkm_subdev *subdev = &sb->subdev; + struct nvkm_device *device = subdev->device; int ret; /* Start falcon */ @@ -149,11 +150,13 @@ nvkm_secboot_falcon_run(struct nvkm_secboot *sb) /* If mail...

...device, 0x200, sb->enable_mask, 0x0); + } + + return 0; +} + +int +nvkm_secboot_falcon_reset(struct nvkm_secboot *sb) +{ + int ret; + + ret = nvkm_secboot_falcon_disable(sb); + if (ret) + return ret; + + ret = nvkm_secboot_falcon_enable(sb); + if (ret) + return ret; + + return 0; +} + +/** + * nvkm_secboot_falcon_run - run the Falcon that will perform secure boot + * + * This function is to be called after all chip-specific preparations have + * been completed. It will start the falcon to perform secure boot, wait for + * it to halt, and report if an error occurred. + */ +int +nvkm_secboot_falcon_run(struct nvk...

...secure boot @@ -99,6 +100,9 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) if (ret) goto done; + /* Disable interrupts as we will poll for the HALT bit */ + nvkm_mc_intr_mask(sb->subdev.device, sb->devidx, false); + /* Start the HS bootloader */ ret = nvkm_secboot_falcon_run(sb); if (ret) -- 2.10.0

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...ret) - goto done; + goto end; /* Load the HS bootloader into the falcon's IMEM/DMEM */ gm200_secboot_load_hs_bl(gsb, &bl_desc, bl_desc_size); @@ -1122,17 +1122,9 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, /* Start the HS bootloader */ ret = nvkm_secboot_falcon_run(&gsb->base); if (ret) - goto done; - -done: - /* Restore the original DMA addresses */ - vma_addr = flcn64_to_u64(desc->code_dma_base) - vma.offset; - desc->code_dma_base.lo = lower_32_bits(vma_addr); - desc->code_dma_base.hi = upper_32_bits(vma_addr); - vma_addr = flcn64_to_u64(...

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

...boot/priv.h index ce0f3c87212b..2a4c4d5a3c90 100644 --- a/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -44,6 +44,175 @@ int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_device *, int nvkm_secboot_falcon_reset(struct nvkm_secboot *); int nvkm_secboot_falcon_run(struct nvkm_secboot *); +/* + * + * LS blob structures + * + */ + +/** + * struct lsf_ucode_desc - LS falcon signatures + * @prd_keys: signature to use when the GPU is in production mode + * @dgb_keys: signature to use when the GPU is in debug mode + * @b_prd_present: whether the production key...

.../* Reset the falcon and make it ready to run the HS bootloader */ + ret = gm200_secboot_setup_falcon(gsb); + if (ret) + goto done; + + /* Load the HS bootloader into the falcon's IMEM/DMEM */ + gm200_secboot_load_hs_bl(gsb, &bl_desc, bl_desc_size); + + /* Start the HS bootloader */ + ret = nvkm_secboot_falcon_run(&gsb->base); + if (ret) + goto done; + +done: + /* Restore the original DMA addresses */ + vma_addr = flcn64_to_u64(desc->code_dma_base) - vma.offset; + desc->code_dma_base.lo = lower_32_bits(vma_addr); + desc->code_dma_base.hi = upper_32_bits(vma_addr); + vma_addr = flcn64_to_u64(...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

...e ASUS Z97 Mainboard Nvidia GTX970 2.587816] nouveau 0000:01:00.0: fifo: read fault at 00ffba0000 engine 1f [] client 12 [PMU] reason 0d [REGION_VIOLATION] on channel -1 [0000000000 unknown] [ 2.687724] nouveau 0000:01:00.0: timeout at drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c:145/nvkm_secboot_falcon_run()! [ 2.687736] nouveau 0000:01:00.0: fifo: write fault at 000030d000 engine 05 [BAR3] client 08 [HOST_CPU_NB] reason 0d [REGION_VIOLATION] on channel -1 [00ffbf5000 unknown] [ 2.687752] nouveau 0000:01:00.0: fifo: write fault at 0000011000 engine 05 [BAR3] client 08 [HOST_CPU_NB] reason 0d [R...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA