search for: nvkm_secboot_falcon_pmu

...352.c index a7213542..00095ef8 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) } } + /* reset the PMU if needed */ + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { + struct nvkm_pmu *pmu = subdev->device->pmu; + if (pmu) { + ret = nvkm_subdev_init(&pmu->subdev); + if (ret < 0) { + nvkm_error(subdev, "Failed to reset PMU\n"); + return ret; + } + }...

Hi Alexandre, On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: [snip] > +static const char * > +managed_falcons_names[] = { > + [NVKM_SECBOOT_FALCON_PMU] = "PMU", > + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", "<reserved>" perhaps ? we already have one invalid below. > + [NVKM_SECBOOT_FALCON_FECS] = "FECS", > + [NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS", > +...

...au/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -108,6 +108,7 @@ gm20b_secboot_new(struct nvkm_device *device, int index, struct gm200_secboot *gsb; struct nvkm_acr *acr; + *psb = NULL; acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT(NVKM_SECBOOT_FALCON_PMU)); if (IS_ERR(acr)) @@ -116,10 +117,8 @@ gm20b_secboot_new(struct nvkm_device *device, int index, acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; + if (!gsb) return -ENOMEM; - } *psb = &gsb->base;...

...: > On 01/21/2016 10:09 PM, Emil Velikov wrote: >> Hi Alexandre, >> >> On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: >> >> [snip] >>> +static const char * >>> +managed_falcons_names[] = { >>> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >>> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", >> "<reserved>" perhaps ? we already have one invalid below. > Does <reserved> really mean: "we don't want to tell you?" here? :) > That or we have...

On 01/21/2016 10:09 PM, Emil Velikov wrote: > Hi Alexandre, > > On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: > > [snip] >> +static const char * >> +managed_falcons_names[] = { >> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", > "<reserved>" perhaps ? we already have one invalid below. Does <reserved> really mean: "we don't want to tell you?" here? :) > >> + [NVKM_SECB...

...ice, int index, 105 struct nvkm_secboot **psb) 106 { 107 int ret; 108 struct gm200_secboot *gsb; 109 struct nvkm_acr *acr; 110 111 acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | 112 BIT(NVKM_SECBOOT_FALCON_PMU)); 113 if (IS_ERR(acr)) 114 return PTR_ERR(acr); 115 /* Support the initial GM20B firmware release without PMU */ 116 acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); 117 118 gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);...

...t; --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) > } > } > > + /* reset the PMU if needed */ > + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && > + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { > + struct nvkm_pmu *pmu = subdev->device->pmu; > + if (pmu) { > + ret = nvkm_subdev_init(&pmu->subdev); > + if (ret < 0) { > + nvkm_error(subdev, "Failed to reset PMU\n"...

...au/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -108,6 +108,7 @@ gm20b_secboot_new(struct nvkm_device *device, int index, struct gm200_secboot *gsb; struct nvkm_acr *acr; + *psb = NULL; acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT(NVKM_SECBOOT_FALCON_PMU)); if (IS_ERR(acr)) @@ -116,10 +117,8 @@ gm20b_secboot_new(struct nvkm_device *device, int index, acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; + if (!gsb) return -ENOMEM; - } *psb = &gsb->base;...

...au/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -108,6 +108,7 @@ gm20b_secboot_new(struct nvkm_device *device, int index, struct gm200_secboot *gsb; struct nvkm_acr *acr; + *psb = NULL; acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT(NVKM_SECBOOT_FALCON_PMU)); if (IS_ERR(acr)) @@ -116,10 +117,8 @@ gm20b_secboot_new(struct nvkm_device *device, int index, acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; + if (!gsb) return -ENOMEM; - } *psb = &gsb->base;...

...au/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -108,6 +108,7 @@ gm20b_secboot_new(struct nvkm_device *device, int index, struct gm200_secboot *gsb; struct nvkm_acr *acr; + *psb = NULL; acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT(NVKM_SECBOOT_FALCON_PMU)); if (IS_ERR(acr)) @@ -116,10 +117,8 @@ gm20b_secboot_new(struct nvkm_device *device, int index, acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; + if (!gsb) return -ENOMEM; - } *psb = &gsb->base;...

...au/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -108,6 +108,7 @@ gm20b_secboot_new(struct nvkm_device *device, int index, struct gm200_secboot *gsb; struct nvkm_acr *acr; + *psb = NULL; acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | BIT(NVKM_SECBOOT_FALCON_PMU)); if (IS_ERR(acr)) @@ -116,10 +117,8 @@ gm20b_secboot_new(struct nvkm_device *device, int index, acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); - if (!gsb) { - psb = NULL; + if (!gsb) return -ENOMEM; - } *psb = &gsb->base;...

...WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKM_SECURE_BOOT_H__ +#define __NVKM_SECURE_BOOT_H__ + +#include <core/subdev.h> + +enum nvkm_secboot_falcon { + NVKM_SECBOOT_FALCON_PMU = 0, + NVKM_SECBOOT_FALCON_RESERVED = 1, + NVKM_SECBOOT_FALCON_FECS = 2, + NVKM_SECBOOT_FALCON_GPCCS = 3, + NVKM_SECBOOT_FALCON_END = 4, + NVKM_SECBOOT_FALCON_INVALID = 0xffffffff, +}; + +/** + * @falcon_id: falcon that will perform secure boot + * @base: base IO address of the falcon performing...

...mil Velikov wrote: >>> Hi Alexandre, >>> >>> On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: >>> >>> [snip] >>>> +static const char * >>>> +managed_falcons_names[] = { >>>> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >>>> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", >>> "<reserved>" perhaps ? we already have one invalid below. >> Does <reserved> really mean: "we don't want to tell you?" here? :) >>...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the